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#rockbox log for 2016-08-07

00:10:46 Quit ender` (Quit: Don't worry about the world coming to an end today. It's already tomorrow in Australia.)
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14:25:39pamaurygevaerts: I just a hit a weird bug, libusb_control_transfer simply refuses to send requests with more than 4096 of data, any idea why ? I don't think the standard imposes such a limitation
14:26:04pamauryand the libusb doc does not say anything about it either afaict
14:30:14pamauryhum apparently this is a "known" limitation of libusb, that is not written anywhere
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14:37:13pamaurythey could at least put in the doc or the headers
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18:04:04pamauryhum, again TCSM0 does not seem to be accessible from its physical address, this looks completely random!
18:11:45*pamaury finally understands
18:12:02pamaurythe AHB1 bus needs to be ungated, this is funny
18:20:10pamaurythis is a bit ridiculous, it's as if the processor was saying "oh please can you give this data ?" and then "answering himself, oh you want this data, here it is"
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18:54:37*pamaury spots a potential bug in mips mmu code
18:54:43pamaurythis code is absolute crap
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19:55:16wodzpamaury: I am not sure mips mmu code in rockbox was ever used actually
19:55:40pamauryI realized local_flush_tlb() is broken because it also blasts wired entries, defeating the whole point!
19:56:28pamaurywodz: I think I asked already but I am confused now. If I create TLB entries with virtual address in kseg0, they will be used by the cpu ? Because the MIPS doc seems to say they won't
19:57:33pamauryI am asking because local_flush_tlb create entries from 0x80000000 and on, assuming they won't be matched against
19:58:36wodzpamaury: I answered already that this two commented lines doesn't make any sense IMO
19:58:55pamauryah ok, I thought they didn't make sense but for other reasons
19:59:24pamaurymap_address is completely wrong, it only create one entry thus can only map 8K of memory
19:59:40pamaurywodz: also I solved my usb problem
20:00:39wodzpamaury: This code looks like semi-random copy paste from linux kernel where it is used differently
20:00:54wodzpamaury: was it libusb limitation or something else?
20:01:50pamauryyeah libusb limits control transfers to 4k
20:02:05pamauryI filled a bug so that it gets documented somewhere, took me a while to figure it out
20:03:28wodzwhile I see that control transfer >4k is a bit of stretch, standard does not say anything about size limitiation IIRC
20:06:15pamauryin fact it's because Windows limits control transfers to 4k, and more generally the UHCI has a hardware limitation that also limits it to 4k. Thus 4k looks like a safe limit
20:07:23 Join alexweissman [0] (
20:09:04wodzpamaury: did you test safe read/write in hwstub on jz?
20:10:40pamaurynot yet, I have been playing with rockbox bootloader and figuring out the mmu
20:12:11 Quit alexweissman (Ping timeout: 276 seconds)
20:14:34pamaurybut I will try now I think
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20:18:04pamaurywodz: why is there so much copy and paste in the atj exception code ?
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20:20:22pamaurywodz: also wouldn't it make sense to implement the safe read/write recovery in asm/mips/system.S ? Because right now the code is in two places and copy/pasted several times
20:23:20pamaurywodz: other question, since eret clears cp 0 hazard, is it really necessary to have ehb in:
20:23:20pamaury mtc0 k1, C0_EPC
20:23:20pamaury ehb
20:23:20DBUGEnqueued KICK pamaury
20:23:20pamaury eret
20:37:26pamauryhum maybe not, the official docs says the hazard is cleared after reading EPC indeed
20:38:15pamaurynot sure how it plays with interlock
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21:18:48 Join kapplejacks [0] (445451ef@gateway/web/freenode/ip.
21:19:08kapplejackshey yall! got an error code im trying to get help trouble shooting, does someone know of an error meaning page?
21:19:16kapplejacksthe error is ATA Error -11
21:22:36pamaurydepends on the target
21:23:57kapplejackssorry about not including that, its an Apple Ipod 5.5 with a 250GB mSATA upgrade
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21:24:36kapplejacksusing 3.13 version of rockbox as well
21:26:30pamauryhum, I don't know anything about apple ipod, I can try to lookup the error but hopefully someone else will answer
21:29:44kapplejacksis there not like an error code definition page?
21:30:54kapplejacksand its interesting because when i had the original 1.8MM spinny disk drive in the ipod it worked just fine, was able to load rockbox and listen to music. Replaced with the SSD and it loads the apple software just fine it only gives that ata error -11 when booting rockbox
21:31:24 Part skrzyp ("WeeChat 1.4")
21:31:51pamauryno, the errors depend on each driver, because we have some many different targets
21:34:22kapplejacksinteresting, good to know. will try updating my google search with some tactful keywords
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21:34:26pamauryI can't find what the error corresponds to, I am afraid you'll have to wait for someone who knows the ipod better
21:35:53kapplejacksfound this
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21:41:04kapplejacksnever done a patch update, is there a wiki or how to article?
21:45:06pamaurywell before applying a patch, I would try the development builds, because 3.13 is very old
21:45:23wodzpamaury: re copy paste - exceptions are regularly spaced 0x200 bytes and you cannot reclaim (easily) this space anyway
21:45:25pamaurythat's assuming the problem is in the main binary and not the bootloader
21:45:45pamaurywodz: I know, but code copy and paste is not nice at all imo
21:47:01wodzpamaury: you can have branch here and there and single exception service routine in case of hwstub.
21:48:13pamauryI don't know how ipod bootloaders work, but assuming the problem is not in the bootloader, you can try to download the ipod video build from this page and put it on your device, simply extract it at the root, it should overwrite the .rockbox directory
21:52:02wodzpamaury: When I was implementing safe read/write for mips, atj was the only mips target. Moving it to asm/mips/something is good thing if you will reuse this code for jz
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21:54:30pamaurywodz: that's what I plan to do
21:54:50pamauryyou'll see my work on gerrit when I push it, feel free to comment if you think I am not doing the right thing ;)
21:55:52kapplejacksso i did what Pamaury suggested and i now get ATA Error -32
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21:57:50pamaurykapplejacks: I am sorry I don't have anything else to suggest, maybe a modified build will work but an ipod expert would really be more helpful than me :)
21:58:17pamaurywodz: I figured why the TCSM0 is sometimes available by its physical address or not
21:58:37kapplejacksi feel, i appreciate the help though, hopefully an Ipod expert chimes in
21:59:23pamaurypeople tend to read the logs, if you stay logged in (try several days because of time zones and week-end) someone might help
21:59:39pamaurywodz: I need to enable the AHB1 bus
22:00:03pamauryin the end I wonder how many cycles it takes to access the TCSM0 when you do that, I find it quite funny
22:01:25wodzpamaury: I was somewhat inspired by the quote form See mips run that original mips designer felt spacing between exception addresses is plenty :-)
22:02:00wodzpamaury: so access to tcm0 goes through ahb-to-ahb bridge?
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22:05:20kapplejacksill be waiting lol
22:06:47pamaury_wodz: yeah if you access address 0xb32b000, it will go through the internal bus (AHB0 I guess), then to AHB1 then to cpu again ^^
22:07:21wodzpamaury_: sounds pretty slow
22:08:22pamaury_wodz: yeah but the point is that I will use this address only for EBASE and then the first thing the handler does is a long jump to the normal address again
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22:30:31CtcpIgnored 1 channel CTCP requests in 0 seconds at the last flood
22:30:31*pamaury has a bug somewhere
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22:37:53*wodz asks pamaury to smash his bug
22:38:26*pamaury is trying, but the bug is not easily found
22:44:22pamaurywodz: what will be the exception raised if I access 0x80000000 when it's not mapped
22:44:53wodzmaybe bus error?
22:45:55pamauryso it goes through the general exception vector ?
22:46:50wodzI think so
22:49:33pamauryhum, I am super confused,
22:49:56pamauryassuming my blinking led code work in the exception vector, not exception is raised on invalid access
22:50:16wodzpamaury: read or write?
22:50:19pamauryso something must be wrong, but EBASE value is correct, code is at the correct place afaict, AHB1 is enabled
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22:53:38wodzI can't remember from the top of my head (and considering red wine taken) but read or write of unmappped address doesn't raise exception. See mips run should have a clue which
22:54:58pamauryso it does what ?
22:55:11*pamaury tries syscall, at least this raises something
22:58:43pamauryhum, interesting, if I ask hwstub to jump directly at the address of the blinking code, it works
22:59:01pamaurybut if I use the uncached address that corresponds to the physical address of tcsm0, it doesn't
22:59:51 Part [Saint] ("Part")
23:00:00wodzsmells like xburst weirdness
23:00:44pamaurythis is highly bizarre because I have done successful EBASE test using such address
23:03:32pamauryok so it seems to work with syscall
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23:06:52pamauryhum, I am a bit puzzled, if I access address 0, it triggers an exceptin
23:07:10pamaurybut addresses like 0x80000000 or 0xb0000000 don't
23:08:14pamauryor maybe those are reported by interrupts, I didn't think about that, I didn't write an interrupt handler
23:09:44wodzare you sure mem controller doesn't by default return something on hw address 0? Maybe it triggers some interrupt or just hang?
23:09:49 Nick ElliotAlderson is now known as [Saint] (~hayden@rockbox/staff/saint)
23:10:47pamauryit does not return anything
23:10:51pamauryso either hang or interrupt
23:10:57pamaurybut I masked interrupts so....
23:12:19pamauryI think I am done for today, I'll resume tomorrow
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23:38:25 Nick [Saint] is now known as ElliotAlderson (~hayden@rockbox/staff/saint)
23:39:44satdavHi you going to be updating rockbox soon
23:40:23pamaurywe are planning to do a release soon hopefully
23:40:37satdavpamaury, that would be good
23:40:45satdavdoes rockbox work on Debain or windows
23:43:02pamaurywhat do you mean ? the installer ?
23:43:11satdavpamaury, yes
23:43:49pamaurythe installer works on linux, mac and windows, with a few exceptions for a few targets I tink
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