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On Wed, 14 Aug 2002, Nielsen Linus (ext) wrote:

> What makes you think that the SH1 on the Archos is a 5V device? It isn't. It
> is 3V (or 3.3, I don't remember).

Arghhh!

All my assumptions based on the schematic naming the DRAM device an
'IS41C16105'! But looking at the photos from inside (after all I've not
opened my AJP6 yet) I can see that in fact it's an 'IS41LV16105'! Nice,
nice, having it at 3.3V makes this stuff a lot easier!

OK, next step. Look for (mostly) pin-compatible 4Mx16 modules with a CAS
width of 10 lines (A0-A9) or less. As mentioned, there are a lot of
manufacturers for this, but it seems they stop production/delivery these
days (f.e. Samsung).

F.e. Mitsubishi has a device 'M5M465160DTP-6' which would be great for our
purposes. Only (minor) issue is that some pins changed their location on
the case (mainly the control pins CAS, RAS, W etc.), but that's no issue
for me.

I don't dare thinking about what changes to the firmware would be
necessary to support _that_ amount of memory :-)

Interested in helping? Watch out for chips in TSOP-II with 50 pins with
the following features:

- 3.3V supply (yyyyess :-))
- 64Mbit storage
- 16 data pins
- CAS=10 lines (A0-A9)
- 4k/64 ms refresh
- FP (fast page) mode (maybe EDO works OK, too)

Can anybody tell me why the Recorder contains a 1Mx16 chip with 1k/16ms
refresh (the K4E151612D) instead of the 4k/64ms refresh chip (K4E171612D)
which would consume about 40% less power (288 mW instead of 468 mW)? OK,
it'd need two more address pins, but that's not an issue on the board, is
it? For the 4Mx16 chips there exist such chips, too (saw it at Samsung)
having a 8k/64 ms refresh with a CAS=9 lines (A0-A8) and an additional
A12 (RAS=A0-A12).

bye for now,
- Matthias

-- 
                    "To get control over people, make them trust you.
                                            To make people trust you
                      don't try to tell them the truth about history
                 but make happen what you told them about the future."

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