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On Thu, 22 Aug 2002 17:36:05 +0200, Sven Karlsson wrote:
> Hi again,
>
> > and every instruction from the RAM anyway. We have no cache.
>
>
> I perfectly know that. In fact, caches have little to do with this.

Yes, they do. If you want fewer memory accesses you will have to use
either a cache or sleep between the memory accesses. This is a RISC
without a cache.

> So the net outcome is shorter code, better register usage, and
> fewer memory accesses. All contributing to the power usage.

Yes, the power usage will be lower _if_ the CPU can do something good
with the time it saves, i.e sleep or loop in a cache. Otherwise it
will still spend its time fetching NOP's from the same RAM that we
saved us some accesses from.

> Anyway, I'll keep my big mouth shut for a while now.

Please don't. These types of discussions are almost always fruitful.

/Linus

-- 
Linus Nielsen Feltzing, linus_at_haxx.se on 2002-08-22

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