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Hi, all. Would somebody be willing to enlighten me with regards to any
the following points? I've looked through the code and the project
research notes, but I've been unable to figure them out on my own. Sorry
if they're obvious. I'm not familiar with the architecture of these sorts
of devices.

(*) What's the SH-1's serial interface hooked up to?

(*) Which pins on the SH-1 control the interrupts?

(*) There doesn't seem to be any cache on the SH-1. Rather, the on-chip
RAM is merely another part of main memory. Is this correct?

(*) The DMA capabilities of the SH-1 allow direct access between on-chip
RAM and memory-mapped devices. Are these capabilities used and, if so,
how?

(*) Is there DMA between the off-chip RAM and the hard drive? I figure's
there's got to be, but...?

Thanks!

 - Carlo

• Next message: Mike Payson: "Re: cvs: docs BATTERY-FAQ,1.10,1.11"
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• Reply: Linus Nielsen Feltzing: "Re: [Qs] serial port; interrupts; memory structure"
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