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Carlo Martino wrote:
> (*) What's the SH-1's serial interface hooked up to?

The SC0 tx pin is connected to the MAS for sending MP3 data.

> (*) Which pins on the SH-1 control the interrupts?

PB0-3 and PA0-3, if I remember correctly. Why?

> (*) There doesn't seem to be any cache on the SH-1. Rather, the on-chip
> RAM is merely another part of main memory. Is this correct?

Yes, that is correct.

> (*) The DMA capabilities of the SH-1 allow direct access between on-chip
> RAM and memory-mapped devices. Are these capabilities used and, if so,
> how?

We use it to feed the serial interface with data when playing music.

> (*) Is there DMA between the off-chip RAM and the hard drive? I figure's
> there's got to be, but...?

No, the CPU has to do the ATA transfers, because the hardware design
forces us to swap the byte order of the 16-bit data.

/Linus

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• In reply to: Carlo Martino: "[Qs] serial port; interrupts; memory structure"
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