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Rockbox mail archiveSubject: Re: RAM size: 8MB (who uses less than that?)Re: RAM size: 8MB (who uses less than that?)
From: Matthias Wächter <matthias_at_waechter.wiz.at>
Date: Fri, 17 Jan 2003 09:34:32 +0100 (CET) Hi guys, I'm sorry that was in German. Let me translate. On Fri, 17 Jan 2003, Uwe Freese wrote: > I already though we wouldn't get your docs these days ;) It's just time. I have a lot to do since my first child is born in April, especially in my flat, at work designing a network IC and with my diploma theses. > I already ordered "Micron 50ns EDO" for 5 EUR + tax + p&p, and at > another store Hynix 60ns EDO for 9 EUR + tax + p&p. The Micron ones are > expected to be delivered by tomorrow or the day after, with a little > luck I can do the mod at the weekend. Cool! I'm expecting your experiences (with your recorder)! > On my search for the memories I saw the refresh value in some data > sheets and that's the only point I don't get. There are 4k and 8k > refresh types of 8MByte (4Mx16) RAMs and the built-in 2MByte (1Mx16) > has 1k refresh. That's simple. Assume you have 'n' address lines on the RAM which are not enough to address the total 'm' address lines for 4M or 1M (x16). For 4Mx16 m=22, for 1Mx16 m=20. These 'm' address lines are multiplexed on the 'n' address lines of the DRAM, and for the muxing RAS and CAS are used. The main question is: How is the splitting between RAS and CAS access done? At the current 1Mx16 with m=20 and n=10 it's simple: The first 10 address lines (higher) are transferred with the RAS cycle, the second part (lower) address lines are transferred with the CAS cycle. With the 4M x 16 there are different possibilities. In theory for m=22 a value of 11 for n would have been enough, and that was what I expected to get. But I saw very soon that neither these chips exist nor the SH-1 would support them: The SH-1 can only shift between RAS and CAS access by 8, 9, or 10 address lines, so it would be fatal to use such a RAM with the DRAM controller of the SH-1 (and IMO they don't exist either). Instead we have to search for RAMs taking the most significant 12 addresses at RAS cycle time, so for the CAS cycle only the least significant 10 addresses are transferred. The SH-1 is already set up for 10 bit shift (see above) for address lines. The RAMs will have 12 address pins which is of course the higher value of the two. > Somehow this means, x thousand times per y milliseconds there has to be > a refresh. With larger memories the value x is always higher. Both > memory types ordered by me are 4k refresh cycle types what would be OK > according to your docs. What would happen if the DRAM would have 8k > refresh cycles? Would the CPU then support this DRAM? From the RAS/CAS splitting also the number of refresh cycles can be directly calculated: Usually the DRAMs support RAS-only refresh, this means roughly that for a refresh cycle a normal access cycle is started but only the RAS part is finished. So the memory area is read and refreshed but not output to the data pins because there was no CAS cycle. If the DRAM uses 12 address pins for RAS access you get a total of 4k refresh cycles for the whole memory, and the data sheet also reflects the maximum time for a complete refresh to not lose data. The original RAM soldered in the AJB has a RAS=10 bit so we have a total of 1k refresh cycles. If you have a 4Mx16 DRAM with 8k refresh this means that the RAM uses 13 address pins for RAS and only 9 address pins for CAS. Don't ask me whether this will work in a AJB (of course the pinning will be different then as well, anyway Rockbox would have to change the DRAM controller configuration then to get support for the complete DRAM without memory area aliasing by only shifting 9 address pins at CAS cycles. That's the short version. :-) > You write "The address shift for CAS access must be 10 bit.". Hmm? ;-) I hope you get the point if you read the above paragraphs. I will look to update the docs. > Are the values given for the Micron (see attached data sheet)? Great data sheet compared to my Hynix one! The data sheet precisely reflects the number of address pins used for RAS and CAS and how it relates to the refresh cycles. BTW: If you have less refresh cycles: You have less performance loss of the DRAM controller (for constant total refresh time) which is an advantage, the disadvantage is that the chip refreshes large memory areas at the same time so the refresh current consumption is larger than with more refresh cycles for smaller memory areas. > If everything goes well I will finally take some pictures of the > recorder mods and give appropriate additional description for it. Great. I will link to your page then. > P.S: Have you seen my Alarm-Mod yet? :-) > http://www.uwe-freese.de/rockbox/ Yes, I got in on the ML. My player doesn't have an RTC, in general I think about going for a newer model. Do you know: Does the FM recorder have an RTC, too? In general I'd like to enhance HW mods. Small patches for making the OFF key lockable. In addition I'd like to patch the Flash to get completely rid of the Jukebox firmware :-) Sehr Wus, - Matthias -- "To get control over people, make them trust you. To make people trust you don't try to tell them the truth about history but make happen what you told them about the future."Received on 2003-01-17 Page template was last modified "Tue Sep 7 00:00:02 2021" The Rockbox Crew -- Privacy Policy |