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Subject: Re: AW: JB not starting with remote pin connected ?
From: Matthias.Klumpp_at_gmx.de
Date: 2004-06-22


Hi Sophana,

first of all many many thanks. That explanation helped me now a lot to
understand what happens.

Please have a look below, I did some more comments and clarifications.

Greetings

Matthias

> >Well, maybe you will not believe it, but it works perfectly in my
> >application.
> >If you do e.g. a PSPICE simulation, you will see - no problem.
> >
> It is normal. A NPN transistor is a piece of silicium with 3 connected
> parts: N,P,N
> The P is the base (always in the middle). the 2 other N are the
> collector and emiter. their size are not the same, that's why one is
> called collector and the other emiter.
> If you invert the collector and emiter, the transistor effect will still
> work, but it is not designed to work like that.
>
> So your scheme is not open collector but it is open emitter.

In fact it is (but it behaves like a OC except the low level is not 0V but
0,7V).
Summarizing your comment it would mean:
It (might) work both ways, but would be better to make it an open emitter
(assuming I want to continue with this schematic), because at least the
trans. is used the way it was designed for.

> Note that a "real" open collector scheme has a resistor between the UC
> and the base, to limit the current. without that, your UC could be
> damaged.

Yeah, ok. I just explained a part of the circuit.
In reality there is a 1k resist. between base and the uC's UART output.
I've choosen 1k, to get most close to the 0,7V level on the output of the
transistor.

> Are you sure that your high level on remote pin is applied before the
> archos dc power?

No, I'm not sure.

> and there is no transistion during the boot?

Well, that's the point.
I had a more close look to the signal. In fact there is a short send command
on the UART (I already discovered the buggy line of code).
So resuming. When I was holding the UART pin low, during initialisation of
my SW, I was electrically supressing the serial communication.
Effect was, that it worked, but I was not changing the behaviour by its
root, but by its symptom ;-))

> Note that I use 5v instead of 3.3v. I don't know if that does count.

I was once told (as I remember by Steve Russell, who did a AJB remote), that
applying 5V to the JB's remote pin could damage it.
That was the reason I was thinking about a OC level shifter.

If you apply 5V direct to the remote input of the JB, there were no damages
?

> >I'm running with 9600 Baud (JB Studio).
> >How is it possible to transmit with different Baud rates ?????
> >
> simply change the serial bitrate in the rockbox serial init.

Serial init means, the Settings or some init inside the Rockbox ?
As I know, the default is 9600Bd, that is also used with the original Archos
SW.
Why did you change the default ?
Your remote control is not anymore compatible with JB's with original SW,
isn't it ?

> >Ok, but we don't have TTL inside the JB.
> All modern chips (above 3.3v) are ttl compatible.
> Vil=0,8v
> Vih=2v
> maybe 2.5v chips io are also ttl compatible.

Ah, so my low level of 0,7V is maybe too close to Vil, that might cause
communication problems in some models.......
I think, I should modify that OC stage to soemthing that has a real 0V low
state....

> >>If you don't sink high current a simple diode would do the same.
> >How ?
> >
> any low signal diode like the 1n4148 will do the same.
> If the UC pin drives a 0, the voltage will be sinked to 0.7v
> if it drives 1, the diode will block and it won't drive anything.
> As there is no charge in your application, the transistor is useless.

I see, 100% correct.
When I was designing that PNP stage, I was not knowing about that 0,7V low
level I now do have.

> >Why do I have to apply 0,7V on the JB's remote pin to make it boot
> >correctly ?
> >
> can you try 5v pullup instead of 3.3v?
> I can assure you it does work in my car.

As I mentioned above, it was not really that I needed to apply low level to
the remote input, I just was overwriting the faulty serial communication of
my SW.

Finilazing:
I think I have to get a low level that is lower than 0,7V to assure a
correct low level recognition in the JB.

What do you think would be better:
- Simply connecting the UART 5V directly to the remote pin (without OC stage
at all) ?
- Designing a double npn transistor stage with last trans. as "real" OC ?

Please remember:
If I use npn transistors, I will need 2 of them to get the correct logic on
the JB remote inp.
Atmel uC's are able to have outputs configured as OC, but not the pin that
is configured as UART. The pins do have 2 possible configurations. If you
use the one as UART TX, you don't have access to the out port configuration
register to make it a OC.
As i know, there is also no way to invert the UART logic.

Many thanks again,

that was clarifying some stuff I guess I once heard at the
University.....long time ago ;-))

-- 
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Sent by: Matthias Klumpp
E-Mail : Matthias.Klumpp_at_gmx.de
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