The thought is scary to have to rewrite the scheduler and queues since they depend on IRQ protection as well as most pcm code. This would not be a small undertaking to have to implement all that stuff as "kernel calls". A change in basic architechture would have to involve all the CPUs imo or we'd basically have different kernels for ARM alone and that not really very rockbox-like. :)

FYI: I put up a patch that does a basic GPIO interrupt enabling and scrollwheel blink so maybe you know of a few pointers about what's going on? Details are there.
  ----- Original Message -----
  From: Antonius Hellmann
  To: Michael Sevakis ; Rockbox development
  Sent: Wednesday, May 09, 2007 12:18 PM
  Subject: Re: PPs running in supervisor mode

  Yes, this is correct: "In User mode, the control bits of the CPSR are protected from change, so only the condition code flags of the CPSR can be changed. In other (privileged) modes the entire CPSR can be changed." If the supervisor mode is the reason for the troubles, then I think it is worth, to modify the software.
    ----- Original Message -----
    From: Michael Sevakis
    To: Rockbox development
    Sent: Wednesday, May 09, 2007 5:40 PM
    Subject: Re: PPs running in supervisor mode

    Wouldn't software interrupts be needed to call code to switch to a supervisor mode when needed? I _am_ rather new to ARM and such but it's my educated guess atm based on our other big CPU. I fear major complication from it.
      ----- Original Message -----
      From: Antonius Hellmann
      To: Rockbox development
      Sent: Wednesday, May 09, 2007 2:03 AM
      Subject: PPs running in supervisor mode

      One idea, why we have these troubles with interrupt handling on the PP devices is, that probably the supervisor mode has some issues with interrupt switching? I understand, that the supervisor mode makes it easy to do register manipulations. But it might be more safe to run the rockbox application code in user mode.
Received on 2007-05-09