Rockbox mail archiveSubject: Re: Sansa (PP502x?) GPIO interrupts in rockbox software
Re: Sansa (PP502x?) GPIO interrupts in rockbox software
From: Michael Sevakis <jethead71_at_sbcglobal.net>
Date: Wed, 9 May 2007 22:56:15 -0400
Experimental results follow...some seem will rephrase what you already said. Now my comment in my FS task is out of sync :).
CPU_INT_EN functions as both ack and disable. Setting a bit any number of times when the corresponding bit is set in the *_STAT register has no effect other than to ack the interrupt. I suspect some are edge sensitive and may not recur if the IRQ is not acked. GPIO is probably level sensitive and interrupts will continue without acking or changing the *_LEV setting. Setting a bit disables the interrupt when it is NOT set at the time of the interrupt. Of course, non-interrupt code should only be able to set the bit(s) when the *_STAT bits are 0 so it disables it since it's not interrupt context.
CPU_INT_STAT never shows bits set for "higher" interrupts when they occur such as HI_MASK (bit 30).
IIOW we ack/disable on the most particular *_EN register and check for it on the most particular *_STAT register.
Disabling various GPIO interrupts: Setting CPU_INT_CLR = HI_MASK or CPU_INT_HI_CLR = GPIO_MASK has no effect. Use GPIOx_INT_EN &= ~mask to disable them.
Check all bits and running the routines for all interrupts flagged in the *_STAT register at the time irq() is called seem very important. This may be refined and simply checking the GPIOx_INT_STAT as well as If...else if for the LO interrupts may be adequate. This scheme could be compatible with all PP and I'd like to have someone volunteer to check things on iPods, etc. Some obviously must get a CPU_HI_INT_STAT for GPIO or the iPod scrollwheels wouldn't work. PP5024 does not as described previously.
That's what I've got so far ... I'll figure out more as needed.
----- Original Message -----
I evaluated the cop interrupts in the current rockbox software:
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