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Subject: Sansa: avoid channel swapping issuesSansa: avoid channel swapping issues
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From: Antonius Hellmann <antonius.hellmann_at_gmx.de>
Date: Sat, 19 May 2007 10:14:11 +0200
Based on an idea of jhMikeS I modified svn code (i2s-pp.c) in the following way:
// IISFIFO_CFG |= 0x33; /* 12 slots full/empty config */
/* Bit2-3, Bit6-7 seem to have no meaning */
IISFIFO_CFG |= 0x22; /* 8 slots full/empty config */
which solves the channel swapping issues. The modification triggers the interrupt already when 8 slots are empty, giving the system additional 45.3usec to execute the fiq without the FIFO running empty. With current frequency setting the cache releases the bus in time to execute the next fiq. The drawback is, that 50% more fiq calls are issued. But the fiq handler itself has some performance tuning potential.
Received on 2007-05-19
Date: Sat, 19 May 2007 10:14:11 +0200
Based on an idea of jhMikeS I modified svn code (i2s-pp.c) in the following way:
// IISFIFO_CFG |= 0x33; /* 12 slots full/empty config */
/* Bit2-3, Bit6-7 seem to have no meaning */
IISFIFO_CFG |= 0x22; /* 8 slots full/empty config */
which solves the channel swapping issues. The modification triggers the interrupt already when 8 slots are empty, giving the system additional 45.3usec to execute the fiq without the FIFO running empty. With current frequency setting the cache releases the bus in time to execute the next fiq. The drawback is, that 50% more fiq calls are issued. But the fiq handler itself has some performance tuning potential.
Received on 2007-05-19
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