.file "fft-ffmpeg.c" .text .align 2 .global pass .type pass, %function pass: @ args = 0, pretend = 0, frame = 32 @ frame_needed = 0, uses_anonymous_args = 0 stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} mov r1, r1, asl #2 sub sp, sp, #36 str r1, [sp, #8] ldr r3, [sp, #8] ldr ip, .L13 mov r1, r2, asl #4 str r1, [sp, #12] add r0, r0, r1 add r1, r3, ip #APP ldmia r0, {r5,r6} mov fp, r2, asl #3 add r0, r0, fp #APP ldmia r0, {r7,r8} mov r2, r2, asl #5 rsb r2, fp, r2 str r2, [sp, #16] ldr ip, [sp, #16] rsb r3, r8, r6 rsb r2, r5, r7 rsb r0, ip, r0 add r4, r7, r5 add r6, r6, r8 #APP ldmia r0, {r9,sl} add r9, r4, r9 add sl, r6, sl sub r4, r9, r4, asl #1 sub r6, sl, r6, asl #1 #APP stmia r0, {r9,sl} add r0, fp, r0 #APP ldmia r0, {r9,sl} add r9, r3, r9 add sl, r2, sl sub r7, r9, r3, asl #1 sub r8, sl, r2, asl #1 #APP stmia r0, {r9,sl} add r0, fp, r0 #APP stmia r0, {r4,r6} add r0, fp, r0 #APP stmia r0, {r7,r8} rsb r0, ip, r0 add r0, r0, #8 #APP ldmia r1, {r4, ip} ldr r2, [sp, #12] add r0, r2, r0 #APP ldmia r0, {r9,sl} smull r3, r8, ip, r9 rsb r6, r9, #0 smlal r3, r8, r4, sl smull r3, r6, r4, r6 smlal r3, r6, ip, sl add r0, fp, r0 mov r2, r8, asl #1 #APP ldmia r0, {r9,sl} smull lr, r3, ip, r9 rsb r7, sl, #0 smlal lr, r3, r4, r7 smull lr, r7, ip, sl smlal lr, r7, r4, r9 mov r3, r3, asl #1 add r2, r2, r3 add r6, r6, r7 ldr r3, [sp, #16] mov r6, r6, asl #1 sub r8, r2, r8, asl #2 sub r7, r6, r7, asl #2 rsb r0, r3, r0 #APP ldmia r0, {r9,sl} add r9, r2, r9 add sl, r6, sl sub r4, r9, r2, asl #1 sub r6, sl, r6, asl #1 #APP stmia r0, {r9,sl} add r0, fp, r0 #APP ldmia r0, {r9,sl} add r9, r7, r9 add sl, r8, sl sub r7, r9, r7, asl #1 sub r8, sl, r8, asl #1 #APP stmia r0, {r9,sl} add r0, fp, r0 #APP stmia r0, {r4,r6} add r0, fp, r0 #APP stmia r0, {r7,r8} ldr ip, [sp, #8] add lr, ip, r1 add r3, ip, lr ldr r1, [sp, #16] mov r5, r3 mov r2, ip, asl #1 add r3, ip, r3 rsb r0, r1, r0 str r2, [sp, #28] str r3, [sp, #24] .L2: add r3, r0, #8 #APP ldmia lr, {r4, ip} ldr r0, [sp, #12] add r3, r0, r3 #APP ldmia r3, {r9,sl} smull r2, r8, ip, r9 rsb r6, r9, #0 smlal r2, r8, r4, sl smull r2, r6, r4, r6 smlal r2, r6, ip, sl add r3, fp, r3 mov r1, r8, asl #1 #APP ldmia r3, {r9,sl} smull r0, r2, ip, r9 rsb r7, sl, #0 smlal r0, r2, r4, r7 smull r0, r7, ip, sl smlal r0, r7, r4, r9 mov r2, r2, asl #1 add r1, r1, r2 add r6, r6, r7 ldr r2, [sp, #16] mov r6, r6, asl #1 sub r8, r1, r8, asl #2 sub r7, r6, r7, asl #2 rsb r3, r2, r3 #APP ldmia r3, {r9,sl} add r9, r1, r9 add sl, r6, sl sub r4, r9, r1, asl #1 sub r6, sl, r6, asl #1 #APP stmia r3, {r9,sl} add r3, fp, r3 #APP ldmia r3, {r9,sl} add r9, r7, r9 add sl, r8, sl sub r7, r9, r7, asl #1 sub r8, sl, r8, asl #1 #APP stmia r3, {r9,sl} add r3, fp, r3 #APP stmia r3, {r4,r6} add r3, fp, r3 #APP stmia r3, {r7,r8} rsb r3, r2, r3 add r3, r3, #8 #APP ldmia r5, {r4, ip} ldr r0, [sp, #12] add r3, r0, r3 #APP ldmia r3, {r9,sl} smull r2, r8, ip, r9 rsb r6, r9, #0 smlal r2, r8, r4, sl smull r2, r6, r4, r6 smlal r2, r6, ip, sl add r3, fp, r3 mov r1, r8, asl #1 #APP ldmia r3, {r9,sl} smull r0, r2, ip, r9 rsb r7, sl, #0 smlal r0, r2, r4, r7 smull r0, r7, ip, sl smlal r0, r7, r4, r9 mov r2, r2, asl #1 add r1, r1, r2 add r6, r6, r7 ldr r2, [sp, #16] mov r6, r6, asl #1 sub r8, r1, r8, asl #2 sub r7, r6, r7, asl #2 rsb r3, r2, r3 #APP ldmia r3, {r9,sl} add r9, r1, r9 add sl, r6, sl sub r4, r9, r1, asl #1 sub r6, sl, r6, asl #1 #APP stmia r3, {r9,sl} add r3, fp, r3 #APP ldmia r3, {r9,sl} add r9, r7, r9 add sl, r8, sl sub r7, r9, r7, asl #1 sub r8, sl, r8, asl #1 #APP stmia r3, {r9,sl} add r3, fp, r3 #APP stmia r3, {r4,r6} add r3, fp, r3 #APP stmia r3, {r7,r8} ldr r0, [sp, #28] ldr ip, [sp, #24] ldr r1, .L13+4 add ip, ip, r0 rsb r2, r0, ip cmp r2, r1 ldr r2, [sp, #16] str ip, [sp, #24] rsb r0, r2, r3 ldr r3, [sp, #28] add lr, lr, r3 add r5, r5, r3 bcc .L2 ldr ip, .L13 cmp lr, ip bls .L7 ldr r1, [sp, #8] rsb r3, r1, #0 rsb r2, r1, lr rsb r3, r1, r3 str r3, [sp, #4] rsb r3, r1, r2 str r3, [sp, #20] mov r5, r2 .L6: add r3, r0, #8 #APP ldmia lr, {r4, ip} ldr r0, [sp, #12] add r3, r0, r3 #APP ldmia r3, {r9,sl} smull r2, r8, r4, r9 rsb r6, r9, #0 smlal r2, r8, ip, sl smull r2, r6, ip, r6 smlal r2, r6, r4, sl add r3, fp, r3 mov r1, r8, asl #1 #APP ldmia r3, {r9,sl} smull r0, r2, r4, r9 rsb r7, sl, #0 smlal r0, r2, ip, r7 smull r0, r7, r4, sl smlal r0, r7, ip, r9 mov r2, r2, asl #1 add r1, r1, r2 add r6, r6, r7 ldr r2, [sp, #16] mov r6, r6, asl #1 sub r8, r1, r8, asl #2 sub r7, r6, r7, asl #2 rsb r3, r2, r3 #APP ldmia r3, {r9,sl} add r9, r1, r9 add sl, r6, sl sub r4, r9, r1, asl #1 sub r6, sl, r6, asl #1 #APP stmia r3, {r9,sl} add r3, fp, r3 #APP ldmia r3, {r9,sl} add r9, r7, r9 add sl, r8, sl sub r7, r9, r7, asl #1 sub r8, sl, r8, asl #1 #APP stmia r3, {r9,sl} add r3, fp, r3 #APP stmia r3, {r4,r6} add r3, fp, r3 #APP stmia r3, {r7,r8} rsb r3, r2, r3 add r3, r3, #8 #APP ldmia r5, {r4, ip} ldr r0, [sp, #12] add r3, r0, r3 #APP ldmia r3, {r9,sl} smull r2, r8, r4, r9 rsb r6, r9, #0 smlal r2, r8, ip, sl smull r2, r6, ip, r6 smlal r2, r6, r4, sl add r3, fp, r3 mov r1, r8, asl #1 #APP ldmia r3, {r9,sl} smull r0, r2, r4, r9 rsb r7, sl, #0 smlal r0, r2, ip, r7 smull r0, r7, r4, sl smlal r0, r7, ip, r9 mov r2, r2, asl #1 add r1, r1, r2 add r6, r6, r7 ldr r2, [sp, #16] mov r6, r6, asl #1 sub r8, r1, r8, asl #2 sub r7, r6, r7, asl #2 rsb r3, r2, r3 #APP ldmia r3, {r9,sl} add r9, r1, r9 add sl, r6, sl sub r4, r9, r1, asl #1 sub r6, sl, r6, asl #1 #APP stmia r3, {r9,sl} add r3, fp, r3 #APP ldmia r3, {r9,sl} add r9, r7, r9 add sl, r8, sl sub r7, r9, r7, asl #1 sub r8, sl, r8, asl #1 #APP stmia r3, {r9,sl} add r3, fp, r3 #APP stmia r3, {r4,r6} add r3, fp, r3 #APP stmia r3, {r7,r8} ldr ip, [sp, #20] ldr r0, [sp, #4] ldr r1, [sp, #28] add ip, ip, r0 add r2, r1, ip str ip, [sp, #20] ldr ip, .L13 ldr r1, [sp, #16] cmp r2, ip ldr r2, [sp, #4] rsb r0, r1, r3 add lr, lr, r2 add r5, r5, r2 bhi .L6 .L7: add sp, sp, #36 ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} .L14: .align 2 .L13: .word sincos_lookup0 .word sincos_lookup0+4096 .size pass, .-pass .align 2 .type fft4_dispatch, %function fft4_dispatch: @ args = 0, pretend = 0, frame = 0 @ frame_needed = 0, uses_anonymous_args = 0 @ link register save eliminated. stmfd sp!, {r4, r5, r6, r7, r8} @ lr needed for prologue #APP ldmia r0, {r1-r8} add r1,r1,r3 sub r3,r1,r3, lsl #1 sub r7,r7,r5 add r5,r7,r5, lsl #1 add r1,r1,r5 sub r5,r1,r5, lsl #1 add r2,r2,r4 sub r4,r2,r4, lsl #1 add r12,r6,r8 sub r6,r6,r8 sub r8,r4,r7 add r4,r4,r7 sub r7,r3,r6 add r3,r3,r6 sub r6,r2,r12 add r2,r2,r12 stmia r0, {r1-r8} ldmfd sp!, {r4, r5, r6, r7, r8} bx lr .size fft4_dispatch, .-fft4_dispatch .align 2 .global fft16 .type fft16, %function fft16: @ args = 0, pretend = 0, frame = 0 @ frame_needed = 0, uses_anonymous_args = 0 stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, lr} #APP ldmia r0, {r1-r8} add r1,r1,r3 sub r3,r1,r3, lsl #1 sub r7,r7,r5 add r5,r7,r5, lsl #1 add r1,r1,r5 sub r5,r1,r5, lsl #1 add r2,r2,r4 sub r4,r2,r4, lsl #1 add r12,r6,r8 sub r6,r6,r8 sub r8,r4,r7 add r4,r4,r7 sub r7,r3,r6 add r3,r3,r6 sub r6,r2,r12 add r2,r2,r12 stmia r0, {r1-r8} add lr, r0, #32 mov ip, r0 #APP add ip, ip, #16 ldmia lr!, {r1,r2,r3,r4,r5,r6,r7,r8} add r1,r1,r3 sub r3,r1,r3,lsl #1 add r2,r2,r4 sub r4,r2,r4,lsl #1 add sl,r5,r7 sub r7,r5,r7 add r5,r6,r8 sub r8,r6,r8 stmdb lr!, {r7,r8} sub r6,sl,r1 add r1,sl,r1 add r2,r2,r5 sub r5,r2,r5,lsl #1 ldmia ip,{r7,r8} add r7,r7,r5 sub r5,r7,r5,lsl #1 add r8,r8,r6 sub r6,r8,r6,lsl #1 stmdb lr!, {r3,r4,r5,r6} stmia ip,{r7,r8} sub ip,ip, #16 ldmia ip,{r7,r8} add r7,r7,r1 sub r1,r7,r1,lsl #1 add r8,r8,r2 sub r2,r8,r2,lsl #1 stmia ip,{r7,r8} stmdb lr, {r1,r2} add r7, ip, #40 #APP ldmia r7, {r7,r8} add r9, ip, #56 #APP ldmia r9, {r9,sl} ldr r3, .L19 #APP smull r2, lr, r3, r7 mov lr, lr, asl #1 #APP smull r2, r1, r3, r8 mov r1, r1, asl #1 #APP smull r2, r7, r3, r9 mov r7, r7, asl #1 #APP smull r4, r2, r3, sl mov r2, r2, asl #1 rsb r4, r2, r7 rsb r6, lr, r1 add r7, r7, r2 add lr, lr, r1 add r4, lr, r4 add r6, r6, r7 sub lr, r4, lr, asl #1 sub r7, r6, r7, asl #1 add ip, ip, #8 #APP ldmia ip, {r9,sl} add r9, r4, r9 add sl, r6, sl sub r4, r9, r4, asl #1 sub r6, sl, r6, asl #1 #APP stmia ip, {r9,sl} add ip, ip, #16 #APP ldmia ip, {r9,sl} add r9, r7, r9 add sl, lr, sl sub r7, r9, r7, asl #1 sub r8, sl, lr, asl #1 #APP stmia ip, {r9,sl} add ip, ip, #16 #APP stmia ip, {r4,r6} add ip, ip, #16 #APP stmia ip, {r7,r8} add sl, r0, #64 #APP ldmia sl, {r1-r8} add r1,r1,r3 sub r3,r1,r3, lsl #1 sub r7,r7,r5 add r5,r7,r5, lsl #1 add r1,r1,r5 sub r5,r1,r5, lsl #1 add r2,r2,r4 sub r4,r2,r4, lsl #1 add r12,r6,r8 sub r6,r6,r8 sub r8,r4,r7 add r4,r4,r7 sub r7,r3,r6 add r3,r3,r6 sub r6,r2,r12 add r2,r2,r12 stmia sl, {r1-r8} add lr, r0, #96 #APP ldmia lr, {r1-r8} add r1,r1,r3 sub r3,r1,r3, lsl #1 sub r7,r7,r5 add r5,r7,r5, lsl #1 add r1,r1,r5 sub r5,r1,r5, lsl #1 add r2,r2,r4 sub r4,r2,r4, lsl #1 add r12,r6,r8 sub r6,r6,r8 sub r8,r4,r7 add r4,r4,r7 sub r7,r3,r6 add r3,r3,r6 sub r6,r2,r12 add r2,r2,r12 stmia lr, {r1-r8} ldmia sl, {r5,r6} ldmia lr, {r7,r8} rsb r3, r8, r6 rsb r2, r5, r7 add r4, r7, r5 add r6, r6, r8 #APP ldmia r0, {r9,sl} add r9, r4, r9 add sl, r6, sl sub r4, r9, r4, asl #1 sub r6, sl, r6, asl #1 #APP stmia r0, {r9,sl} add r0, r0, #32 #APP ldmia r0, {r9,sl} add r9, r3, r9 add sl, r2, sl sub r7, r9, r3, asl #1 sub r8, sl, r2, asl #1 #APP stmia r0, {r9,sl} add r0, r0, #32 #APP stmia r0, {r4,r6} add r0, r0, #32 #APP stmia r0, {r7,r8} sub r7, r0, #16 #APP ldmia r7, {r7,r8} add r9, r0, #16 #APP ldmia r9, {r9,sl} ldr r3, .L19 #APP smull r2, ip, r3, r7 mov ip, ip, asl #1 #APP smull r2, r1, r3, r8 mov r1, r1, asl #1 #APP smull r2, r7, r3, r9 mov r7, r7, asl #1 #APP smull lr, r2, r3, sl mov r2, r2, asl #1 rsb r4, r2, r7 rsb r6, ip, r1 add r7, r7, r2 add ip, ip, r1 add r4, ip, r4 add r6, r6, r7 sub ip, r4, ip, asl #1 sub r7, r6, r7, asl #1 sub r0, r0, #80 #APP ldmia r0, {r9,sl} add r9, r4, r9 add sl, r6, sl sub r4, r9, r4, asl #1 sub r6, sl, r6, asl #1 #APP stmia r0, {r9,sl} add r0, r0, #32 #APP ldmia r0, {r9,sl} add r9, r7, r9 add sl, ip, sl sub r7, r9, r7, asl #1 sub r8, sl, ip, asl #1 #APP stmia r0, {r9,sl} add r0, r0, #32 #APP stmia r0, {r4,r6} add r0, r0, #32 #APP stmia r0, {r7,r8} sub r9, r0, #40 #APP ldmia r9, {r9,sl} ldr r2, .L19+4 ldr r3, .L19+8 #APP smull r1, r8, r2, r9 rsb r6, r9, #0 smlal r1, r8, r3, sl smull r1, r6, r3, r6 smlal r1, r6, r2, sl sub r9, r0, #8 mov r4, r8, asl #1 #APP ldmia r9, {r9,sl} smull ip, r1, r2, r9 rsb r7, sl, #0 smlal ip, r1, r3, r7 smull ip, r7, r2, sl smlal ip, r7, r3, r9 mov r1, r1, asl #1 add r6, r6, r7 add r4, r4, r1 mov r6, r6, asl #1 sub r8, r4, r8, asl #2 sub r7, r6, r7, asl #2 sub r0, r0, #104 #APP ldmia r0, {r9,sl} add r9, r4, r9 add sl, r6, sl sub r4, r9, r4, asl #1 sub r6, sl, r6, asl #1 #APP stmia r0, {r9,sl} add r0, r0, #32 #APP ldmia r0, {r9,sl} add r9, r7, r9 add sl, r8, sl sub r7, r9, r7, asl #1 sub r8, sl, r8, asl #1 #APP stmia r0, {r9,sl} add r0, r0, #32 #APP stmia r0, {r4,r6} add r0, r0, #32 #APP stmia r0, {r7,r8} sub r9, r0, #16 #APP ldmia r9, {r9,sl} ldr r2, .L19+8 ldr r3, .L19+4 #APP smull r1, r8, r2, r9 rsb r6, r9, #0 smlal r1, r8, r3, sl smull r1, r6, r3, r6 smlal r1, r6, r2, sl add r9, r0, #16 mov r4, r8, asl #1 #APP ldmia r9, {r9,sl} smull ip, r1, r2, r9 rsb r7, sl, #0 smlal ip, r1, r3, r7 smull ip, r7, r2, sl smlal ip, r7, r3, r9 mov r1, r1, asl #1 add r6, r6, r7 add r4, r4, r1 mov r6, r6, asl #1 sub r8, r4, r8, asl #2 sub r7, r6, r7, asl #2 sub r0, r0, #80 #APP ldmia r0, {r9,sl} add r9, r4, r9 add sl, r6, sl sub r4, r9, r4, asl #1 sub r6, sl, r6, asl #1 #APP stmia r0, {r9,sl} add r0, r0, #32 #APP ldmia r0, {r9,sl} add r9, r7, r9 add sl, r8, sl sub r7, r9, r7, asl #1 sub r8, sl, r8, asl #1 #APP stmia r0, {r9,sl} add r0, r0, #32 #APP stmia r0, {r4,r6} add r0, r0, #32 #APP stmia r0, {r7,r8} ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, pc} .L20: .align 2 .L19: .word 1518500250 .word 1984016189 .word 821806413 .size fft16, .-fft16 .align 2 .global ff_fft_calc_c .type ff_fft_calc_c, %function ff_fft_calc_c: @ args = 0, pretend = 0, frame = 0 @ frame_needed = 0, uses_anonymous_args = 0 str lr, [sp, #-4]! ldr r2, .L23 mov r3, r0, asl #2 sub sp, sp, #4 add r3, r3, r2 mov r0, r1 mov lr, pc ldr pc, [r3, #-8] add sp, sp, #4 ldmfd sp!, {pc} .L24: .align 2 .L23: .word fft_dispatch .size ff_fft_calc_c, .-ff_fft_calc_c .align 2 .type fft8_dispatch, %function fft8_dispatch: @ args = 0, pretend = 0, frame = 0 @ frame_needed = 0, uses_anonymous_args = 0 stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, lr} #APP ldmia r0, {r1-r8} add r1,r1,r3 sub r3,r1,r3, lsl #1 sub r7,r7,r5 add r5,r7,r5, lsl #1 add r1,r1,r5 sub r5,r1,r5, lsl #1 add r2,r2,r4 sub r4,r2,r4, lsl #1 add r12,r6,r8 sub r6,r6,r8 sub r8,r4,r7 add r4,r4,r7 sub r7,r3,r6 add r3,r3,r6 sub r6,r2,r12 add r2,r2,r12 stmia r0, {r1-r8} add lr, r0, #32 mov ip, r0 #APP add ip, ip, #16 ldmia lr!, {r1,r2,r3,r4,r5,r6,r7,r8} add r1,r1,r3 sub r3,r1,r3,lsl #1 add r2,r2,r4 sub r4,r2,r4,lsl #1 add sl,r5,r7 sub r7,r5,r7 add r5,r6,r8 sub r8,r6,r8 stmdb lr!, {r7,r8} sub r6,sl,r1 add r1,sl,r1 add r2,r2,r5 sub r5,r2,r5,lsl #1 ldmia ip,{r7,r8} add r7,r7,r5 sub r5,r7,r5,lsl #1 add r8,r8,r6 sub r6,r8,r6,lsl #1 stmdb lr!, {r3,r4,r5,r6} stmia ip,{r7,r8} sub ip,ip, #16 ldmia ip,{r7,r8} add r7,r7,r1 sub r1,r7,r1,lsl #1 add r8,r8,r2 sub r2,r8,r2,lsl #1 stmia ip,{r7,r8} stmdb lr, {r1,r2} add r7, ip, #40 #APP ldmia r7, {r7,r8} add r9, ip, #56 #APP ldmia r9, {r9,sl} ldr r3, .L27 #APP smull r2, r0, r3, r7 mov r0, r0, asl #1 #APP smull r2, r1, r3, r8 mov r1, r1, asl #1 #APP smull r2, r7, r3, r9 mov r7, r7, asl #1 #APP smull lr, r2, r3, sl mov r2, r2, asl #1 rsb r4, r2, r7 rsb r6, r0, r1 add r7, r7, r2 add r0, r0, r1 add r4, r0, r4 add r6, r6, r7 sub r0, r4, r0, asl #1 sub r7, r6, r7, asl #1 add ip, ip, #8 #APP ldmia ip, {r9,sl} add r9, r4, r9 add sl, r6, sl sub r4, r9, r4, asl #1 sub r6, sl, r6, asl #1 #APP stmia ip, {r9,sl} add ip, ip, #16 #APP ldmia ip, {r9,sl} add r9, r7, r9 add sl, r0, sl sub r7, r9, r7, asl #1 sub r8, sl, r0, asl #1 #APP stmia ip, {r9,sl} add ip, ip, #16 #APP stmia ip, {r4,r6} add ip, ip, #16 #APP stmia ip, {r7,r8} ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, pc} .L28: .align 2 .L27: .word 1518500250 .size fft8_dispatch, .-fft8_dispatch .align 2 .global fft32 .type fft32, %function fft32: @ args = 0, pretend = 0, frame = 0 @ frame_needed = 0, uses_anonymous_args = 0 stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} mov fp, r0 sub sp, sp, #4 bl fft16 add lr, fp, #128 #APP ldmia lr, {r1-r8} add r1,r1,r3 sub r3,r1,r3, lsl #1 sub r7,r7,r5 add r5,r7,r5, lsl #1 add r1,r1,r5 sub r5,r1,r5, lsl #1 add r2,r2,r4 sub r4,r2,r4, lsl #1 add r12,r6,r8 sub r6,r6,r8 sub r8,r4,r7 add r4,r4,r7 sub r7,r3,r6 add r3,r3,r6 sub r6,r2,r12 add r2,r2,r12 stmia lr, {r1-r8} add r0, fp, #160 #APP add lr, lr, #16 ldmia r0!, {r1,r2,r3,r4,r5,r6,r7,r8} add r1,r1,r3 sub r3,r1,r3,lsl #1 add r2,r2,r4 sub r4,r2,r4,lsl #1 add ip,r5,r7 sub r7,r5,r7 add r5,r6,r8 sub r8,r6,r8 stmdb r0!, {r7,r8} sub r6,ip,r1 add r1,ip,r1 add r2,r2,r5 sub r5,r2,r5,lsl #1 ldmia lr,{r7,r8} add r7,r7,r5 sub r5,r7,r5,lsl #1 add r8,r8,r6 sub r6,r8,r6,lsl #1 stmdb r0!, {r3,r4,r5,r6} stmia lr,{r7,r8} sub lr,lr, #16 ldmia lr,{r7,r8} add r7,r7,r1 sub r1,r7,r1,lsl #1 add r8,r8,r2 sub r2,r8,r2,lsl #1 stmia lr,{r7,r8} stmdb r0, {r1,r2} add r7, lr, #40 #APP ldmia r7, {r7,r8} add r9, lr, #56 #APP ldmia r9, {r9,sl} ldr r3, .L31 #APP smull r2, r0, r3, r7 mov r0, r0, asl #1 #APP smull r2, r1, r3, r8 mov r1, r1, asl #1 #APP smull r2, r7, r3, r9 mov r7, r7, asl #1 #APP smull ip, r2, r3, sl mov r2, r2, asl #1 rsb r4, r2, r7 rsb r6, r0, r1 add r7, r7, r2 add r0, r0, r1 add r4, r0, r4 add r6, r6, r7 sub r0, r4, r0, asl #1 sub r7, r6, r7, asl #1 add lr, lr, #8 #APP ldmia lr, {r9,sl} add r9, r4, r9 add sl, r6, sl sub r4, r9, r4, asl #1 sub r6, sl, r6, asl #1 #APP stmia lr, {r9,sl} add lr, lr, #16 #APP ldmia lr, {r9,sl} add r9, r7, r9 add sl, r0, sl sub r7, r9, r7, asl #1 sub r8, sl, r0, asl #1 #APP stmia lr, {r9,sl} add lr, lr, #16 #APP stmia lr, {r4,r6} add lr, lr, #16 #APP stmia lr, {r7,r8} add lr, fp, #192 #APP ldmia lr, {r1-r8} add r1,r1,r3 sub r3,r1,r3, lsl #1 sub r7,r7,r5 add r5,r7,r5, lsl #1 add r1,r1,r5 sub r5,r1,r5, lsl #1 add r2,r2,r4 sub r4,r2,r4, lsl #1 add r12,r6,r8 sub r6,r6,r8 sub r8,r4,r7 add r4,r4,r7 sub r7,r3,r6 add r3,r3,r6 sub r6,r2,r12 add r2,r2,r12 stmia lr, {r1-r8} add r0, fp, #224 #APP add lr, lr, #16 ldmia r0!, {r1,r2,r3,r4,r5,r6,r7,r8} add r1,r1,r3 sub r3,r1,r3,lsl #1 add r2,r2,r4 sub r4,r2,r4,lsl #1 add ip,r5,r7 sub r7,r5,r7 add r5,r6,r8 sub r8,r6,r8 stmdb r0!, {r7,r8} sub r6,ip,r1 add r1,ip,r1 add r2,r2,r5 sub r5,r2,r5,lsl #1 ldmia lr,{r7,r8} add r7,r7,r5 sub r5,r7,r5,lsl #1 add r8,r8,r6 sub r6,r8,r6,lsl #1 stmdb r0!, {r3,r4,r5,r6} stmia lr,{r7,r8} sub lr,lr, #16 ldmia lr,{r7,r8} add r7,r7,r1 sub r1,r7,r1,lsl #1 add r8,r8,r2 sub r2,r8,r2,lsl #1 stmia lr,{r7,r8} stmdb r0, {r1,r2} add r7, lr, #40 #APP ldmia r7, {r7,r8} add r9, lr, #56 #APP ldmia r9, {r9,sl} ldr r3, .L31 #APP smull r2, r0, r3, r7 mov r0, r0, asl #1 #APP smull r2, r1, r3, r8 mov r1, r1, asl #1 #APP smull r2, r7, r3, r9 mov r7, r7, asl #1 #APP smull ip, r2, r3, sl mov r2, r2, asl #1 rsb r4, r2, r7 rsb r6, r0, r1 add r7, r7, r2 add r0, r0, r1 add r4, r0, r4 add r6, r6, r7 sub r0, r4, r0, asl #1 sub r7, r6, r7, asl #1 add lr, lr, #8 #APP ldmia lr, {r9,sl} add r9, r4, r9 add sl, r6, sl sub r4, r9, r4, asl #1 sub r6, sl, r6, asl #1 #APP stmia lr, {r9,sl} add lr, lr, #16 #APP ldmia lr, {r9,sl} add r9, r7, r9 add sl, r0, sl sub r7, r9, r7, asl #1 sub r8, sl, r0, asl #1 #APP stmia lr, {r9,sl} add lr, lr, #16 #APP stmia lr, {r4,r6} add lr, lr, #16 #APP stmia lr, {r7,r8} mov r1, #256 mov r0, fp mov r2, #8 add sp, sp, #4 ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} b pass .L32: .align 2 .L31: .word 1518500250 .size fft32, .-fft32 .align 2 .global fft64 .type fft64, %function fft64: @ args = 0, pretend = 0, frame = 0 @ frame_needed = 0, uses_anonymous_args = 0 stmfd sp!, {r4, lr} mov r4, r0 bl fft32 add r0, r4, #256 bl fft16 add r0, r4, #384 bl fft16 mov r0, r4 mov r1, #128 mov r2, #16 ldmfd sp!, {r4, lr} b pass .size fft64, .-fft64 .align 2 .global fft128 .type fft128, %function fft128: @ args = 0, pretend = 0, frame = 0 @ frame_needed = 0, uses_anonymous_args = 0 stmfd sp!, {r4, lr} mov r4, r0 bl fft64 add r0, r4, #512 bl fft32 add r0, r4, #768 bl fft32 mov r0, r4 mov r1, #64 mov r2, #32 ldmfd sp!, {r4, lr} b pass .size fft128, .-fft128 .align 2 .global fft256 .type fft256, %function fft256: @ args = 0, pretend = 0, frame = 0 @ frame_needed = 0, uses_anonymous_args = 0 stmfd sp!, {r4, lr} mov r4, r0 bl fft128 add r0, r4, #1024 bl fft64 add r0, r4, #1536 bl fft64 mov r0, r4 mov r1, #32 mov r2, #64 ldmfd sp!, {r4, lr} b pass .size fft256, .-fft256 .align 2 .global fft512 .type fft512, %function fft512: @ args = 0, pretend = 0, frame = 0 @ frame_needed = 0, uses_anonymous_args = 0 stmfd sp!, {r4, lr} mov r4, r0 bl fft256 add r0, r4, #2048 bl fft128 add r0, r4, #3072 bl fft128 mov r0, r4 mov r1, #16 mov r2, #128 ldmfd sp!, {r4, lr} b pass .size fft512, .-fft512 .align 2 .global fft1024 .type fft1024, %function fft1024: @ args = 0, pretend = 0, frame = 0 @ frame_needed = 0, uses_anonymous_args = 0 stmfd sp!, {r4, lr} mov r4, r0 bl fft512 add r0, r4, #4096 bl fft256 add r0, r4, #6144 bl fft256 mov r0, r4 mov r1, #8 mov r2, #256 ldmfd sp!, {r4, lr} b pass .size fft1024, .-fft1024 .align 2 .global fft2048 .type fft2048, %function fft2048: @ args = 0, pretend = 0, frame = 0 @ frame_needed = 0, uses_anonymous_args = 0 stmfd sp!, {r4, lr} mov r4, r0 bl fft1024 add r0, r4, #8192 bl fft512 add r0, r4, #12288 bl fft512 mov r0, r4 mov r1, #4 mov r2, #512 ldmfd sp!, {r4, lr} b pass .size fft2048, .-fft2048 .align 2 .global fft4096 .type fft4096, %function fft4096: @ args = 0, pretend = 0, frame = 0 @ frame_needed = 0, uses_anonymous_args = 0 stmfd sp!, {r4, lr} mov r4, r0 bl fft2048 add r0, r4, #16384 bl fft1024 add r0, r4, #24576 bl fft1024 mov r0, r4 mov r1, #2 mov r2, #1024 ldmfd sp!, {r4, lr} b pass .size fft4096, .-fft4096 .section .rodata .align 2 .type fft_dispatch, %object .size fft_dispatch, 44 fft_dispatch: .word fft4_dispatch .word fft8_dispatch .word fft16 .word fft32 .word fft64 .word fft128 .word fft256 .word fft512 .word fft1024 .word fft2048 .word fft4096 .ident "GCC: (GNU) 4.1.2"