Index: firmware/target/arm/as3525/clock-target.h =================================================================== --- firmware/target/arm/as3525/clock-target.h (revision 21285) +++ firmware/target/arm/as3525/clock-target.h (working copy) @@ -24,8 +24,31 @@ /* returns clock divider, given maximal target frequency and clock reference */ #define CLK_DIV(ref, target) ((ref + target - 1) / target) +/* Choose Selectable Frequencies or Preset Clocking Scheme by uncommenting */ +/* Preset name key=CLOCK_FCLK_PCLK_DBOPCLK. Presets all use synchronous bus*/ -/* Frequency and Bus Settings +/* Default is 248_62_62 FCLK_PCLK_DBOPCLK Synchronous Bus*/ + +//#define CLOCK_248_62_31 /* Default w/31MHz dbop(e200v2 radio) */ + + /* FCLK < 200 allows lower core voltage. See as3525 datasheet p.12 6.2.1 */ +//#define CLOCK_192_64_64 /* OF uses 64 Mhz PCLK */ +//#define CLOCK_192_64_32 /* 64MHz Pclk w/32MHz dbop(e200v2 Radio) */ +//#define CLOCK_195_65_65 /* 65MHz Pclk is the upper limit */ + +//#define CLOCK_SELECT_FREQS /* Select freqs & autoconfigure dividers */ + + + +/* Clock Sources */ +#define AS3525_CLK_MAIN 0 +#define AS3525_CLK_PLLA 1 +//#define AS3525_CLK_PLLB 2 +#define AS3525_CLK_FCLK 3 /* Available as PCLK input only */ + +#if defined CLOCK_SELECT_FREQS + +/* Selectable Frequency and Bus Settings * These bus settings work on the assumption that unboosted performance will be * based on fastbus mode(FCLK == PCLK) at a frequency configured with this file. * Boosted performance defaults to synchronous bus but will be changed to @@ -49,80 +72,81 @@ * have included USB & PLLB for future use but commented them out for now. */ -/* Clock Sources */ -#define AS3525_CLK_MAIN 0 -#define AS3525_CLK_PLLA 1 -//#define AS3525_CLK_PLLB 2 -#define AS3525_CLK_FCLK 3 /* Available as PCLK input only */ -/** ************ Change these to reconfigure clocking scheme *******************/ + +/** ************ Change these to select clocking frequencies ******************/ /* PLL frequencies and settings*/ -#define AS3525_PLLA_FREQ 248000000 /*124,82.7,62,49.6,41.3,35.4 */ - /* FCLK_PREDIV-> *7/8 = 217MHz 108.5 ,72.3, 54.25, 43.4, 36.17 */ - /* *6/8 = 186MHz 93, 62, 46.5, 37.2 */ - /* *5/8 = 155MHz 77.5, 51.67, 38.75 */ +#define AS3525_PLLA_FREQ 248000000 /* 124, 82.7, 62 */ + /* FCLK_PREDIV-> *7/8 = 217MHz 108.5 ,72.3, 54.25 */ + /* *6/8 = 186MHz 93, 62, 46.5 */ + /* *5/8 = 155MHz 77.5, 51.67 */ #define AS3525_PLLA_SETTING 0x261F -//#define AS3525_PLLA_FREQ 384000000 /*192,128,96,76.8,64,54.9,48,42.7,38.4*/ - /* FCLK_PREDIV-> *7/8 = 336MHz 168, 112, 84, 67.2, 56, 48, 42, 37.3*/ - /* *6/8 = 288MHz 144, 96, 72, 57.6, 48, 41.1, */ - /* *5/8 = 240MHz 120, 80, 60, 48, 40 */ +//#define AS3525_PLLA_FREQ 384000000 /* 192, 128, 96, 76.8, 64 */ + /* FCLK_PREDIV-> *7/8 = 336MHz 168, 112, 84, 67.2, 56 */ + /* *6/8 = 288MHz 144, 96, 72, 57.6 */ + /* *5/8 = 240MHz 120, 80, 60 */ //#define AS3525_PLLA_SETTING 0x2630 +//#define AS3525_PLLA_FREQ 390000000 /* 195, 130, 97.5, 78, 65 */ +//#define AS3525_PLLA_SETTING 0x2841 + /* PLLB not used at this time! */ //#define AS3525_PLLB_FREQ //#define AS3525_PLLB_SETTING -#define AS3525_FCLK_PREDIV 0 /* div = (8-n)/8 Enter manually & postdiv will be calculated*/ - /* 0 gives you the PLLA 1st line choices, 1 the 2nd line etc. */ +#define AS3525_FCLK_PREDIV 0 /* div = (8-n)/8 Enter manually & postdiv will + be calculated. 0 gives you the PLLA 1st line + choices, 1 the 2nd line etc. */ -#define AS3525_FCLK_FREQ 248000000 /* Boosted FCLK frequency */ -#define AS3525_DRAM_FREQ 62000000 /* Initial DRAM frequency */ - /* AS3525_PCLK_FREQ != AS3525_DRAM_FREQ/1 will boot to white lcd screen */ -#define AS3525_PCLK_FREQ AS3525_DRAM_FREQ/1 /* PCLK divided from DRAM freq */ -#define AS3525_DBOP_FREQ AS3525_PCLK_FREQ/1 /* DBOP divided from PCLK freq */ +#define AS3525_FCLK_FREQ 248000000 /* Boosted FCLK frequency */ +#define AS3525_DRAM_FREQ 62000000 /* Initial DRAM frequency */ + /* AS3525_PCLK_FREQ != AS3525_DRAM_FREQ/1 will boot to white lcd screen */ +#define AS3525_PCLK_FREQ AS3525_DRAM_FREQ/1 /*PCLK divided from DRAM freq*/ +#define AS3525_DBOP_FREQ AS3525_PCLK_FREQ/1 /*DBOP divided from PCLK freq*/ -/** ****************************************************************************/ +/** ***************************************************************************/ /* Figure out if we need to use asynchronous bus */ #if (AS3525_FCLK_FREQ % AS3525_PCLK_FREQ) -#define ASYNCHRONOUS_BUS /* Boosted mode asynchronous */ +#define ASYNCHRONOUS_BUS /* Boosted mode asynchronous */ #endif -/* Tell the software what frequencies we're running */ -#define CPUFREQ_MAX AS3525_FCLK_FREQ -#define CPUFREQ_DEFAULT AS3525_PCLK_FREQ -#define CPUFREQ_NORMAL AS3525_PCLK_FREQ - /* FCLK */ #define AS3525_FCLK_SEL AS3525_CLK_PLLA -#define AS3525_FCLK_POSTDIV (CLK_DIV((AS3525_PLLA_FREQ*(8-AS3525_FCLK_PREDIV)/8), AS3525_FCLK_FREQ) - 1) /*div=1/(n+1)*/ +#define AS3525_FCLK_POSTDIV (CLK_DIV((AS3525_PLLA_FREQ * \ + (8-AS3525_FCLK_PREDIV)/8), AS3525_FCLK_FREQ) 1) + /*div=1/(n+1)*/ /* PCLK */ #ifdef ASYNCHRONOUS_BUS -#define AS3525_PCLK_SEL AS3525_CLK_PLLA /* PLLA input for asynchronous */ -#define AS3525_PCLK_DIV0 (CLK_DIV(AS3525_PLLA_FREQ, AS3525_DRAM_FREQ) - 1)/*div=1/(n+1)*/ +#define AS3525_PCLK_SEL AS3525_CLK_PLLA /* PLLA input for asynch bus*/ + /*div=1/(n+1)*/ +#define AS3525_PCLK_DIV0 (CLK_DIV(AS3525_PLLA_FREQ, AS3525_DRAM_FREQ)-1) #else -#define AS3525_PCLK_SEL AS3525_CLK_FCLK /* Fclk input for synchronous */ -#define AS3525_PCLK_DIV0 (CLK_DIV(AS3525_FCLK_FREQ, AS3525_DRAM_FREQ) - 1) /*div=1/(n+1)*/ +#define AS3525_PCLK_SEL AS3525_CLK_FCLK /* Fclk input for synch bus */ + /*div=1/(n+1)*/ +#define AS3525_PCLK_DIV0 (CLK_DIV(AS3525_FCLK_FREQ, AS3525_DRAM_FREQ)-1) #endif - /*unable to use AS3525_PCLK_DIV1 != 0 successfuly so far*/ -#define AS3525_PCLK_DIV1 (CLK_DIV(AS3525_DRAM_FREQ, AS3525_PCLK_FREQ) - 1)/* div = 1/(n+1)*/ + /*unable to use AS3525_PCLK_DIV1 != 0 successfuly so far*//* div = 1/(n+1)*/ +#define AS3525_PCLK_DIV1 (CLK_DIV(AS3525_DRAM_FREQ, AS3525_PCLK_FREQ)-1) - /* PCLK as Source */ - #define AS3525_DBOP_DIV (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1) /*div=1/(n+1)*/ + /* PCLK as Source */ /*div=1/(n+1)*/ + #define AS3525_DBOP_DIV (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ)-1) #define AS3525_I2C_PRESCALER CLK_DIV(AS3525_PCLK_FREQ, AS3525_I2C_FREQ) #define AS3525_I2C_FREQ 400000 - #define AS3525_SD_IDENT_DIV ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SD_IDENT_FREQ) / 2) - 1) + #define AS3525_SD_IDENT_DIV ((CLK_DIV(AS3525_PCLK_FREQ, \ + AS3525_SD_IDENT_FREQ) / 2) - 1) #define AS3525_SD_IDENT_FREQ 400000 /* must be between 100 & 400 kHz */ #define AS3525_IDE_SEL AS3525_CLK_PLLA /* Input Source */ -#define AS3525_IDE_DIV (CLK_DIV(AS3525_PLLA_FREQ, AS3525_IDE_FREQ) - 1)/*div=1/(n+1)*/ + /*div=1/(n+1)*/ +#define AS3525_IDE_DIV (CLK_DIV(AS3525_PLLA_FREQ, AS3525_IDE_FREQ)-1) #define AS3525_IDE_FREQ 90000000 /* The OF uses 66MHz maximal freq but sd transfers fail on some players with this limit */ -//#define AS3525_USB_SEL AS3525_CLK_PLLA /* Input Source */ +//#define AS3525_USB_SEL AS3525_CLK_PLLA /* Input Source */ //#define AS3525_USB_DIV /* div = 1/(n=0?1:2n)*/ @@ -145,8 +169,131 @@ #error I2C frequency is too low : clock divider will not fit ! #endif /* AS3525_SD_IDENT_FREQ */ -#if ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SD_IDENT_FREQ) / 2) - 1) >= (1<<8) /* 8 bits */ +#if ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SD_IDENT_FREQ)/2)-1) >= (1<<8) /*8 bits*/ #error SD IDENTIFICATION frequency is too low : clock divider will not fit ! #endif + /* End of CLOCK_SELECT_FREQS Pre Tested Clock Configurations follow */ + + +/* Preconfigured Clock settings: Sync Bus CLOCK_FCLK_PCLOCK_DBOPCLK */ +#elif defined CLOCK_192_64_64 + +#define AS3525_PLLA_SETTING 0x2630 /* AS3525_PLLA_FREQ = 384MHz*/ +#define AS3525_PLLA_FREQ 384000000 +#define AS3525_FCLK_SEL 1 /* AS3525_CLK_PLLA */ +#define AS3525_FCLK_PREDIV 0 /* 384/1 = 384 */ +#define AS3525_FCLK_POSTDIV 1 /* 384/2 = 192*/ +#define AS3525_FCLK_FREQ 192000000 /* Boosted FCLK frequency */ +#define AS3525_PCLK_SEL 3 /* AS3525_CLK_FCLK Sync Bus*/ +#define AS3525_PCLK_DIV0 2 /* 192/3 = 64 */ +#define AS3525_PCLK_DIV1 0 /* 64/1 = 64 */ +#define AS3525_PCLK_FREQ 64000000 +#define AS3525_DBOP_DIV 0 /* 64/1 = 64 */ +#define AS3525_DBOP_FREQ 64000000 +#define AS3525_I2C_PRESCALER 160 /* 64Mhz/160 = 400khz */ +#define AS3525_I2C_FREQ 400000 +#define AS3525_SD_IDENT_DIV 80 /* 64MHz/161 = 397khz */ +#define AS3525_SD_IDENT_FREQ 397000 /* must be between 100 & 400 kHz */ +#define AS3525_IDE_SEL 1 /* Input Source = PLLA */ +#define AS3525_IDE_DIV 4 /* 384Mhz/5 = 76.8 MHz*/ +#define AS3525_IDE_FREQ 76800000 + +#elif defined CLOCK_192_64_32 + +#define AS3525_PLLA_SETTING 0x2630 /* AS3525_PLLA_FREQ = 384MHz*/ +#define AS3525_PLLA_FREQ 384000000 +#define AS3525_FCLK_SEL 1 /* AS3525_CLK_PLLA */ +#define AS3525_FCLK_PREDIV 0 /* 384/1 = 384 */ +#define AS3525_FCLK_POSTDIV 1 /* 384/2 = 192*/ +#define AS3525_FCLK_FREQ 192000000 /* Boosted FCLK frequency */ +#define AS3525_PCLK_SEL 3 /* AS3525_CLK_FCLK Sync Bus*/ +#define AS3525_PCLK_DIV0 2 /* 192/3 = 64 */ +#define AS3525_PCLK_DIV1 0 /* 64/1 = 64 */ +#define AS3525_PCLK_FREQ 64000000 +#define AS3525_DBOP_DIV 1 /* 64/2 = 32 */ +#define AS3525_DBOP_FREQ 32000000 +#define AS3525_I2C_PRESCALER 160 /* 64Mhz/160 = 400khz */ +#define AS3525_I2C_FREQ 400000 +#define AS3525_SD_IDENT_DIV 80 /* 64MHz/161 = 397khz */ +#define AS3525_SD_IDENT_FREQ 397000 /* must be between 100 & 400 kHz */ +#define AS3525_IDE_SEL 1 /* Input Source = PLLA */ +#define AS3525_IDE_DIV 4 /* 384Mhz/5 = 76.8 MHz*/ +#define AS3525_IDE_FREQ 76800000 + +#elif defined CLOCK_248_62_31 + +#define AS3525_PLLA_SETTING 0x261F /* AS3525_PLLA_FREQ = 248MHz*/ +#define AS3525_PLLA_FREQ 248000000 +#define AS3525_FCLK_SEL 1 /* AS3525_CLK_PLLA */ +#define AS3525_FCLK_PREDIV 0 /* 248/1 = 248 */ +#define AS3525_FCLK_POSTDIV 0 /* 248/1 = 248*/ +#define AS3525_FCLK_FREQ 248000000 /* Boosted FCLK frequency */ +#define AS3525_PCLK_SEL 3 /* AS3525_CLK_FCLK Sync Bus*/ +#define AS3525_PCLK_DIV0 3 /* 248/4 = 62 */ +#define AS3525_PCLK_DIV1 0 /* 62/1 = 62 */ +#define AS3525_PCLK_FREQ 62000000 +#define AS3525_DBOP_DIV 1 /* 62/2 = 31 */ +#define AS3525_DBOP_FREQ 31000000 +#define AS3525_I2C_PRESCALER 155 /* 62Mhz/155 = 400khz */ +#define AS3525_I2C_FREQ 400000 +#define AS3525_SD_IDENT_DIV 77 /* 62MHz/155 = 400khz */ +#define AS3525_SD_IDENT_FREQ 400000 /* must be between 100 & 400 kHz */ +#define AS3525_IDE_SEL 1 /* Input Source = PLLA */ +#define AS3525_IDE_DIV 2 /* 248Mhz/3 = 82.67 MHz*/ +#define AS3525_IDE_FREQ 82670000 + + +#elif defined CLOCK_195_65_65 + +#define AS3525_PLLA_SETTING 0x2841 /* AS3525_PLLA_FREQ = 390MHz*/ +#define AS3525_PLLA_FREQ 390000000 +#define AS3525_FCLK_SEL 1 /* AS3525_CLK_PLLA */ +#define AS3525_FCLK_PREDIV 0 /* 390/1 = 390 */ +#define AS3525_FCLK_POSTDIV 1 /* 390/2 = 195*/ +#define AS3525_FCLK_FREQ 195000000 /* Boosted FCLK frequency */ +#define AS3525_PCLK_SEL 3 /* AS3525_CLK_FCLK Sync Bus*/ +#define AS3525_PCLK_DIV0 2 /* 195/3 = 65 */ +#define AS3525_PCLK_DIV1 0 /* 65/1 = 65 */ +#define AS3525_PCLK_FREQ 65000000 +#define AS3525_DBOP_DIV 0 /* 65/1 = 65 */ +#define AS3525_DBOP_FREQ 65000000 +#define AS3525_I2C_PRESCALER 163 /* 65Mhz/163 = 398khz */ +#define AS3525_I2C_FREQ 398000 +#define AS3525_SD_IDENT_DIV 81 /* 65MHz/163 = 398khz */ +#define AS3525_SD_IDENT_FREQ 398000 /* must be between 100 & 400 kHz */ +#define AS3525_IDE_SEL 1 /* Input Source = PLLA */ +#define AS3525_IDE_DIV 4 /* 390Mhz/5 = 78 MHz*/ +#define AS3525_IDE_FREQ 78000000 + + +#else /* Default Clocking Scheme 248_62_62 FCLK_PCLK_DBOPCLK Sync Bus*/ + +#define AS3525_PLLA_SETTING 0x261F /* AS3525_PLLA_FREQ = 248MHz*/ +#define AS3525_PLLA_FREQ 248000000 +#define AS3525_FCLK_SEL 1 /* AS3525_CLK_PLLA */ +#define AS3525_FCLK_PREDIV 0 /* 248/1 = 248 */ +#define AS3525_FCLK_POSTDIV 0 /* 248/1 = 248*/ +#define AS3525_FCLK_FREQ 248000000 /* Boosted FCLK frequency */ +#define AS3525_PCLK_SEL 3 /* AS3525_CLK_FCLK Sync Bus*/ +#define AS3525_PCLK_DIV0 3 /* 248/4 = 62 */ +#define AS3525_PCLK_DIV1 0 /* 62/1 = 62 */ +#define AS3525_PCLK_FREQ 62000000 +#define AS3525_DBOP_DIV 0 /* 62/1 = 62 */ +#define AS3525_DBOP_FREQ 62000000 +#define AS3525_I2C_PRESCALER 155 /* 62Mhz/155 = 400khz */ +#define AS3525_I2C_FREQ 400000 +#define AS3525_SD_IDENT_DIV 77 /* 62MHz/155 = 400khz */ +#define AS3525_SD_IDENT_FREQ 400000 /* must be between 100 & 400 kHz */ +#define AS3525_IDE_SEL 1 /* Input Source = PLLA */ +#define AS3525_IDE_DIV 2 /* 248Mhz/3 = 82.67 MHz*/ +#define AS3525_IDE_FREQ 82670000 + +#endif + +/* Tell the software what frequencies we're running */ +#define CPUFREQ_MAX AS3525_FCLK_FREQ +#define CPUFREQ_DEFAULT AS3525_PCLK_FREQ +#define CPUFREQ_NORMAL AS3525_PCLK_FREQ + #endif /* CLOCK_TARGET_H */