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FS#10184 - Add AMBA bus setting assembler routines to mmu-arm.S(used by: gigabeats,MRobe,Creative,as3525)
Attached to Project:
Rockbox
Opened by Jack Halpin (FlynDice) - Sunday, 03 May 2009, 07:41 GMT+2
Last edited by Jack Halpin (FlynDice) - Friday, 26 June 2009, 04:30 GMT+2
Opened by Jack Halpin (FlynDice) - Sunday, 03 May 2009, 07:41 GMT+2
Last edited by Jack Halpin (FlynDice) - Friday, 26 June 2009, 04:30 GMT+2
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DetailsThis patch adds 3 assembler routines that control the relationship between the AMBA bus and the arm processor. I've placed them in mmu-arm.s because the same control register that is used to set the mmu properties is used to control the bus relationship. Both gigabeats, the MRobe, and the creative ZVm use this file currently and I'd like to use it for the as3525 targets. I have not #ifdef'd them as I believe they should work for those targets also. These are the same bus setting routines the gigabeat fx uses to switch from MAX freq to NORMAL freq. I have not removed anything, only added the 3 routines so I am pretty confident this would not break another target. I don't know that I would trust me though so please take a look!
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This task depends upon
Closed by Jack Halpin (FlynDice)
Friday, 26 June 2009, 04:30 GMT+2
Reason for closing: Fixed
Additional comments about closing: The need for these routines does not exist anymore after FS#10048 was committed.
Friday, 26 June 2009, 04:30 GMT+2
Reason for closing: Fixed
Additional comments about closing: The need for these routines does not exist anymore after
Putting them in mmu-arm.c is only confusing.
In fact, mmu-arm.S already contains only semi-related stuff. We should rather rename it. I don't think these deserve a new file. And I think they should be in a .S, not in a .c.
I thought there is only related stuff : mmu setup, and functions to maintain cache coherency.
MMU is independent of the caches. Also, the icache is not mmu dependent.
For example cachable regions have to be declared in the Translation Table which is looked up by the MMU.
And I think the Memory Management Unit "manages" the caches as well since they are memory; but the BUS clocking mode isn't related to memory at all.