Index: firmware/target/arm/as3525/system-as3525.c
===================================================================
--- firmware/target/arm/as3525/system-as3525.c	(revision 20865)
+++ firmware/target/arm/as3525/system-as3525.c	(working copy)
@@ -229,29 +229,21 @@
     CGU_PROC = 0;           /* fclk 24 MHz */
     CGU_PERI &= ~0x7f;      /* pclk 24 MHz */
 
-    asm volatile(
-        "mrc p15, 0, r0, c1, c0  \n"
-        "orr r0, r0, #0xC0000000 \n" /* asynchronous clocking */
-        "mcr p15, 0, r0, c1, c0  \n"
-        : : : "r0" );
+    CGU_PLLA = AS3525_PLLA_SETTING;  /*  PLLA = 248M */
+    while(!(CGU_INTCTRL & (1<<0)));  /* wait until PLLA is locked */
 
-    CGU_PLLA = AS3525_PLLA_SETTING;
-    while(!(CGU_INTCTRL & (1<<0))); /* wait until PLLA is locked */
+    CGU_PROC = (AS3525_CPU_PREDIV << 2) | 1; /* Div=1,source=PLLA=FCLK 248MHz*/
 
-    CGU_PROC = (AS3525_CPU_PREDIV << 2) | 1;
+    CGU_PERI |= ((3 << 2) | 3); /* div =(3+1)=4, source = Fclk PCLK=62M*/
 
-    CGU_PERI |= ((CLK_DIV(AS3525_PLLA_FREQ, AS3525_PCLK_FREQ) - 1) << 2)
-                | 1; /* clk_in = PLLA */
-
-
-    /* FIXME: dcache will not be active, since the mmu is not running
-     * See arm922t datasheet */
     asm volatile(
         "mov r0, #0               \n"
         "mcr p15, 0, r0, c7, c7   \n" /* invalidate icache & dcache */
         "mrc p15, 0, r0, c1, c0   \n" /* control register */
+        "bic r0, r0, #0xC0000000  \n" /* clear bus bits */
+        "orr r0, r0, #0x40000000  \n" /* synchronous bus  */
         "orr r0, r0, #0x1000      \n" /* enable icache */
-        "orr r0, r0, #4           \n" /* enable dcache */
+        "orr r0, r0, #1<<14       \n" /* enable round robin replacement */
         "mcr p15, 0, r0, c1, c0   \n"
         : : : "r0" );
 
@@ -311,16 +303,31 @@
 #ifdef HAVE_ADJUSTABLE_CPU_FREQ
 void set_cpu_frequency(long frequency)
 {
-    int divider = frequency ? (CPUFREQ_MAX / frequency) : 16 /* minimal */ ;
+    if(frequency == CPUFREQ_MAX)
+    {
+        /* mmu_bus_sync();*/        /* 922CLK = FCLK = (4)PCLK */
+        asm volatile(
+            "mrc p15, 0, r0, c1, c0  \n"
+            "bic r0, r0, #0xc0000000 \n" /* clear bus bits */
+            "orr r0, r0, #0x40000000 \n" /* synchronous clocking */
+            "mcr p15, 0, r0, c1, c0  \n"
+            : : : "r0" );
 
-    if(divider > 16)
-        divider = 16;
-    else if(divider < 1)
-        divider = 1;
+        CGU_PROC &= ~(1 << 2); /* Div=1, FCLK = 248MHz */
+        cpu_frequency = CPUFREQ_MAX;
+    }
+    else
+    {
+        /* mmu_bus_fast();*/             /* 922CLK = PCLK  (62Mhz)   */
+        asm volatile(
+            "mrc p15, 0, r0, c1, c0  \n"
+            "bic r0, r0, #0xC0000000 \n" /* fastbus clocking */
+            "mcr p15, 0, r0, c1, c0  \n"
+            : : : "r0" );
 
-    cpu_frequency = CPUFREQ_MAX / divider;
-
-    CGU_PROC = (CGU_PROC & 0x0f) | ((divider-1) << 4);
+        CGU_PROC |= (1<< 2);        /* Div=2, FCLK=124MHz PCLK=31MHz*/
+        cpu_frequency = CPUFREQ_NORMAL;
+    }
 }
 #endif /* HAVE_ADJUSTABLE_CPU_FREQ */
 #endif /* BOOTLOADER */
Index: firmware/target/arm/as3525/clock-target.h
===================================================================
--- firmware/target/arm/as3525/clock-target.h	(revision 20865)
+++ firmware/target/arm/as3525/clock-target.h	(working copy)
@@ -33,13 +33,13 @@
 
 #define CPUFREQ_MAX             248000000
 
-#define CPUFREQ_DEFAULT         24800000
+#define CPUFREQ_DEFAULT         31000000
 
 #define CPUFREQ_NORMAL          31000000
 
 /* peripherals */
 
-#define AS3525_PCLK_FREQ        65000000
+#define AS3525_PCLK_FREQ        62000000
 
 #define AS3525_IDE_FREQ         90000000