Index: rockbox.20920.target/firmware/target/arm/as3525/system-as3525.c
===================================================================
--- rockbox.20920.target/firmware/target/arm/as3525/system-as3525.c	(revision 20920)
+++ rockbox.20920.target/firmware/target/arm/as3525/system-as3525.c	(working copy)
@@ -241,17 +241,16 @@
     CGU_PROC = (AS3525_CPU_PREDIV << 2) | 1;
 
     CGU_PERI |= ((CLK_DIV(AS3525_PLLA_FREQ, AS3525_PCLK_FREQ) - 1) << 2)
-                | 1; /* clk_in = PLLA */
+                | 3; /* clk_in = FCLK */
 
-
-    /* FIXME: dcache will not be active, since the mmu is not running
-     * See arm922t datasheet */
     asm volatile(
         "mov r0, #0               \n"
-        "mcr p15, 0, r0, c7, c7   \n" /* invalidate icache & dcache */
-        "mrc p15, 0, r0, c1, c0   \n" /* control register */
-        "orr r0, r0, #0x1000      \n" /* enable icache */
-        "orr r0, r0, #4           \n" /* enable dcache */
+        "mcr p15, 0, r0, c7, c7   \n"      /* invalidate icache & dcache */
+        "mrc p15, 0, r0, c1, c0   \n"      /* control register */
+        "bic r0, r0, #3<<30      \n"       /* clear bus bits */
+        "orr r0, r0, #1<<30      \n"       /* synchronous bus clocking */
+        "orr r0, r0, #1<<14       \n"      /* round robin cache replacement */
+        "orr r0, r0, #1<<12       \n"      /* enable icache */
         "mcr p15, 0, r0, c1, c0   \n"
         : : : "r0" );
 
@@ -311,16 +310,30 @@
 #ifdef HAVE_ADJUSTABLE_CPU_FREQ
 void set_cpu_frequency(long frequency)
 {
-    int divider = frequency ? (CPUFREQ_MAX / frequency) : 16 /* minimal */ ;
-
-    if(divider > 16)
-        divider = 16;
-    else if(divider < 1)
+/* 
+   Doing synch clocking, so lets stop pretending we can do any
+   frequency demanded. ARM demands FCLK = PCLK*n, n is an int > 0. So to
+   keep things simple, if frequency parameter >= CPUFREQ_MAX, set FCLK
+   to CPUFREQ_MAX and PCLK to AS3525_PCLK_FREQ. Else set FCLK to
+   CPUFREQ_NORMAL and PCLK to AS3525_PCLK_FREQ/2.
+*/
+    int divider;
+    
+    if (frequency >= CPUFREQ_MAX)
+    {
+        cpu_frequency = CPUFREQ_MAX;
+        /*pclk_frequency = AS3525_PCLK_FREQ;*/
         divider = 1;
-
-    cpu_frequency = CPUFREQ_MAX / divider;
-
-    CGU_PROC = (CGU_PROC & 0x0f) | ((divider-1) << 4);
+        CGU_PERI &= ~(1 << 5); /* Divide PCLK by 1, leave MPMC_CLK at 62MHz */
+    }
+    else
+    {
+        cpu_frequency = CPUFREQ_NORMAL;
+        /*pclk_frequency = AS3525_PCLK_FREQ/2;*/
+        divider = CLK_DIV(CPUFREQ_MAX,CPUFREQ_NORMAL);
+        CGU_PERI |= 1 << 5; /* Divide PCLK by 2, leave MPMC_CLK at 62MHz */
+    }
+    CGU_PROC = (CGU_PROC & 0x0f) | ((divider-1) << 4);    
 }
 #endif /* HAVE_ADJUSTABLE_CPU_FREQ */
 #endif /* BOOTLOADER */
Index: rockbox.20920.target/firmware/target/arm/as3525/clock-target.h
===================================================================
--- rockbox.20920.target/firmware/target/arm/as3525/clock-target.h	(revision 20920)
+++ rockbox.20920.target/firmware/target/arm/as3525/clock-target.h	(working copy)
@@ -33,13 +33,13 @@
 
 #define CPUFREQ_MAX             248000000
 
-#define CPUFREQ_DEFAULT         24800000
+#define CPUFREQ_DEFAULT         62000000
 
-#define CPUFREQ_NORMAL          31000000
+#define CPUFREQ_NORMAL          62000000
 
 /* peripherals */
 
-#define AS3525_PCLK_FREQ        65000000
+#define AS3525_PCLK_FREQ        62000000
 
 #define AS3525_IDE_FREQ         90000000
 
@@ -55,7 +55,7 @@
 #elif   defined(SANSA_FUZE)
 #define AS3525_DBOP_FREQ        8000000
 #elif   defined(SANSA_E200V2)
-#define AS3525_DBOP_FREQ        8000000
+#define AS3525_DBOP_FREQ        AS3525_PCLK_FREQ
 #elif   defined(SANSA_C200V2)
 #define AS3525_DBOP_FREQ        8000000
 #endif