Index: apps/plugins/test_disk.c
===================================================================
--- apps/plugins/test_disk.c	(revision 20931)
+++ apps/plugins/test_disk.c	(working copy)
@@ -32,7 +32,7 @@
 #if (CONFIG_STORAGE & STORAGE_MMC)
 #define TEST_SIZE (20*1024*1024)
 #else
-#define TEST_SIZE (300*1024*1024)
+#define TEST_SIZE (1*1024*1024)
 #endif
 #define TEST_TIME 10 /* in seconds */
 
Index: apps/plugins/SOURCES
===================================================================
--- apps/plugins/SOURCES	(revision 20931)
+++ apps/plugins/SOURCES	(working copy)
@@ -159,3 +159,6 @@
 #endif
 
 md5sum.c
+test_codec.c
+test_disk.c
+test_fps.c
Index: firmware/target/arm/as3525/sansa-e200v2/lcd-e200v2.c
===================================================================
--- firmware/target/arm/as3525/sansa-e200v2/lcd-e200v2.c	(revision 20931)
+++ firmware/target/arm/as3525/sansa-e200v2/lcd-e200v2.c	(working copy)
@@ -108,7 +108,11 @@
 /* DBOP initialisation, do what OF does */
 static void ams3525_dbop_init(void)
 {
+#if 0
     CGU_DBOP = (1<<3) | (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1);
+#else
+    CGU_DBOP = (1<<3) | 0x00; /* DBOP clock == PCLK */
+#endif
 
     DBOP_TIMPOL_01 = 0xe167e167;
     DBOP_TIMPOL_23 = 0xe167006e;
Index: firmware/target/arm/as3525/system-as3525.c
===================================================================
--- firmware/target/arm/as3525/system-as3525.c	(revision 20931)
+++ firmware/target/arm/as3525/system-as3525.c	(working copy)
@@ -229,31 +229,55 @@
     CGU_PROC = 0;           /* fclk 24 MHz */
     CGU_PERI &= ~0x7f;      /* pclk 24 MHz */
 
-    asm volatile(
-        "mrc p15, 0, r0, c1, c0  \n"
-        "orr r0, r0, #0xC0000000 \n" /* asynchronous clocking */
-        "mcr p15, 0, r0, c1, c0  \n"
-        : : : "r0" );
-
     CGU_PLLA = AS3525_PLLA_SETTING;
     while(!(CGU_INTCTRL & (1<<0))); /* wait until PLLA is locked */
 
     CGU_PROC = (AS3525_CPU_PREDIV << 2) | 1;
 
+#ifdef BOOTLOADER
     CGU_PERI |= ((CLK_DIV(AS3525_PLLA_FREQ, AS3525_PCLK_FREQ) - 1) << 2)
                 | 1; /* clk_in = PLLA */
+    asm volatile(
+        "mrc p15, 0, r0, c1, c0  \n"
+        "orr r0, r0, #0xC0000000 \n" /* asynchronous clocking */
+        "mcr p15, 0, r0, c1, c0  \n"
+        : : : "r0" );
 
+#else /* !BOOTLOADER */
 
-    /* FIXME: dcache will not be active, since the mmu is not running
-     * See arm922t datasheet */
+    /* Set up valid clock ratios before setting clock mode */
+#if defined(HAVE_ADJUSTABLE_CPU_FREQ)
+    set_cpu_frequency(CPUFREQ_NORMAL);
+#else /* !HAVE_ADJUSTABLE_CPU_FREQ*/
+    CGU_PROC = (CGU_PROC & 0x0f) | ((CLK_DIV(AS3525_PLLA_FREQ,CPUFREQ_NORMAL)-1) << 4);
+#if !defined(USE_ASYNC_CLOCK_MODE)
+    /* DIV1:0,DIV0:1, i.e. Divide FCLK by 2 */    
+    CGU_PERI = (CGU_PERI & ~(0x7c)) | (1 << 2) | 3; /* clk_in = FCLK */
+#else /* USE_ASYNC_CLOCK_MODE */
+    CGU_PERI |= ((CLK_DIV(AS3525_PLLA_FREQ, AS3525_PCLK_FREQ) - 1) << 2) | 1; /* clk_in = PLLA */
+#endif /* USE_ASYNC_CLOCK_MODE */
+#endif /* !HAVE_ADJUSTABLE_CPU_FREQ */
+/*#define USE_ARM_ASYNC_CLOCK_MODE*/
     asm volatile(
         "mov r0, #0               \n"
-        "mcr p15, 0, r0, c7, c7   \n" /* invalidate icache & dcache */
-        "mrc p15, 0, r0, c1, c0   \n" /* control register */
-        "orr r0, r0, #0x1000      \n" /* enable icache */
-        "orr r0, r0, #4           \n" /* enable dcache */
+        "mcr p15, 0, r0, c7, c7   \n"      /* invalidate icache & dcache */
+        "mrc p15, 0, r0, c1, c0   \n"      /* control register */
+        "bic r0, r0, #3<<30      \n"       /* clear bus bits */
+#if !defined(USE_ARM_ASYNC_CLOCK_MODE)
+        "orr r0, r0, #1<<30      \n"       /* synchronous bus clocking */
+#else
+        "orr r0, r0, #3<<30      \n"       /* asynchronous bus clocking */
+#endif
+#if 1
+        "orr r0, r0, #1<<14       \n"      /* round robin cache replacement */
+        "orr r0, r0, #1<<12       \n"      /* enable icache */
+#else
+        "orr r0, r0, #0x1000      \n"      /* enable icache */
+        "orr r0, r0, #4           \n"      /* enable dcache */
+#endif
         "mcr p15, 0, r0, c1, c0   \n"
         : : : "r0" );
+#endif /* !BOOTLOADER */
 
 #ifdef BOOTLOADER
     sdram_init();
@@ -281,10 +305,6 @@
     fmradio_i2c_init();
 #endif
 #endif /* !BOOTLOADER */
-
-#ifdef HAVE_ADJUSTABLE_CPU_FREQ
-    set_cpu_frequency(CPUFREQ_DEFAULT);
-#endif
 }
 
 void system_reboot(void)
@@ -311,8 +331,46 @@
 #ifdef HAVE_ADJUSTABLE_CPU_FREQ
 void set_cpu_frequency(long frequency)
 {
-    int divider = frequency ? (CPUFREQ_MAX / frequency) : 16 /* minimal */ ;
+#if !defined(USE_ASYNC_CLOCK_MODE)
+/* 
+   Doing synch clocking, so let's stop pretending we can do any
+   frequency demanded. ARM demands FCLK = PCLK*n, n is an int > 0. So
+   to keep things simple, if frequency parameter >= CPUFREQ_MAX, set
+   FCLK to CPUFREQ_MAX and PCLK to FCLK/4. Else set FCLK to
+   CPUFREQ_NORMAL and PCLK to FCLK/2.
+*/
+    if (frequency >= CPUFREQ_MAX)
+    {
+        cpu_frequency = CPUFREQ_MAX;
+        /* Increasing freq, so set bigger PCLK divisor first, then
+           faster FCLK  */
+        /* DIV1=0,DIV0=3, i.e. PCLK= FCLK/4, MPMC_CLK at PCLK  */
+        CGU_PERI = (CGU_PERI & ~(0x7c)) | (3 << 2) | 3;
+        /* FCLK_POST_DIV_SEL=0, FCLK = PLLA */
+        CGU_PROC = 
+            (CGU_PROC & 0x0f) | ((CLK_DIV(AS3525_PLLA_FREQ,CPUFREQ_MAX) - 1) << 4);
+    }
+    else
+    {
+        cpu_frequency = CPUFREQ_NORMAL;
+        /* Decreasing freq, so set slower FLCK first, then
+            smaller PCLK divisor */
+        CGU_PROC = 
+            (CGU_PROC & 0x0f) | ((CLK_DIV(AS3525_PLLA_FREQ,CPUFREQ_NORMAL) - 1) << 4);
+/*#define USE_FCLK_AS_MPMC_CLK*/
+#if defined(USE_FCLK_AS_MPMC_CLK)
+        /* DIV1=1,DIV0=0, i.e. PCLK= FCLK/2,  MPMC_CLK at FCLK */
+        CGU_PERI = (CGU_PERI & ~(0x7c)) | (1 << 6) | 3; /* Doesn't work */
+#else
+        /* DIV1=0,DIV0=1, i.e. PCLK= FCLK/2, MPMC_CLK at PCLK */    
+        CGU_PERI = (CGU_PERI & ~(0x7c)) | (1 << 2) | 3; /* Works */
+#endif
+    }
 
+#else /* USE_ASYNC_CLOCK_MODE */
+    /*int divider = frequency ? (CPUFREQ_MAX / frequency) : 16 *//* minimal */ ;
+    int divider = CLK_DIV(CPUFREQ_MAX,frequency);
+    
     if(divider > 16)
         divider = 16;
     else if(divider < 1)
@@ -321,6 +379,7 @@
     cpu_frequency = CPUFREQ_MAX / divider;
 
     CGU_PROC = (CGU_PROC & 0x0f) | ((divider-1) << 4);
+#endif /* USE_ASYNC_CLOCK_MODE */
 }
 #endif /* HAVE_ADJUSTABLE_CPU_FREQ */
 #endif /* BOOTLOADER */
Index: firmware/target/arm/as3525/clock-target.h
===================================================================
--- firmware/target/arm/as3525/clock-target.h	(revision 20931)
+++ firmware/target/arm/as3525/clock-target.h	(working copy)
@@ -36,9 +36,9 @@
 
 #define CPUFREQ_MAX             248000000
 
-#define CPUFREQ_DEFAULT         24800000
+#define CPUFREQ_DEFAULT         62000000
 
-#define CPUFREQ_NORMAL          31000000
+#define CPUFREQ_NORMAL          62000000
 
 /* peripherals */