diff --git a/firmware/target/arm/as3525/clock-target.h b/firmware/target/arm/as3525/clock-target.h
index 1928f1f..4e0d4c7 100644
--- a/firmware/target/arm/as3525/clock-target.h
+++ b/firmware/target/arm/as3525/clock-target.h
@@ -36,9 +36,9 @@
 
 #define CPUFREQ_MAX             248000000
 
-#define CPUFREQ_DEFAULT         24800000
+#define CPUFREQ_DEFAULT         AS3525_PCLK_FREQ
 
-#define CPUFREQ_NORMAL          31000000
+#define CPUFREQ_NORMAL          AS3525_PCLK_FREQ
 
 /* peripherals */
 
diff --git a/firmware/target/arm/as3525/system-as3525.c b/firmware/target/arm/as3525/system-as3525.c
index a5f34d9..ed5ac76 100644
--- a/firmware/target/arm/as3525/system-as3525.c
+++ b/firmware/target/arm/as3525/system-as3525.c
@@ -231,7 +231,7 @@ void system_init(void)
 
     asm volatile(
         "mrc p15, 0, r0, c1, c0  \n"
-        "orr r0, r0, #0xC0000000 \n" /* asynchronous clocking */
+        "bic r0, r0, #0xC0000000 \n" /* fastbus clocking */
         "mcr p15, 0, r0, c1, c0  \n"
         : : : "r0" );
 
@@ -311,16 +311,34 @@ int system_memory_guard(int newmode)
 #ifdef HAVE_ADJUSTABLE_CPU_FREQ
 void set_cpu_frequency(long frequency)
 {
-    int divider = frequency ? (CPUFREQ_MAX / frequency) : 16 /* minimal */ ;
+    if(frequency == AS3525_PCLK_FREQ)
+    {
+        cpu_frequency = frequency;
+        asm volatile(
+            "mrc p15, 0, r0, c1, c0  \n"
+            "bic r0, r0, #0xC0000000 \n" /* fastbus clocking */
+            "mcr p15, 0, r0, c1, c0  \n"
+            : : : "r0" );
+    }
+    else
+    {
+        int divider = frequency ? (CPUFREQ_MAX / frequency) : 16 /* minimal */ ;
 
-    if(divider > 16)
-        divider = 16;
-    else if(divider < 1)
-        divider = 1;
+        if(divider > 16)
+            divider = 16;
+        else if(divider < 1)
+            divider = 1;
 
-    cpu_frequency = CPUFREQ_MAX / divider;
+        cpu_frequency = CPUFREQ_MAX / divider;
 
-    CGU_PROC = (CGU_PROC & 0x0f) | ((divider-1) << 4);
+        CGU_PROC = (CGU_PROC & 0x0f) | ((divider-1) << 4);
+
+        asm volatile(
+            "mrc p15, 0, r0, c1, c0  \n"
+            "orr r0, r0, #0x40000000 \n" /* synchronous clocking */
+            "mcr p15, 0, r0, c1, c0  \n"
+            : : : "r0" );
+    }
 }
 #endif /* HAVE_ADJUSTABLE_CPU_FREQ */
 #endif /* BOOTLOADER */