From 1ca8bd44944b65680b71e0ce9123e09e78129227 Mon Sep 17 00:00:00 2001 From: =?utf-8?q?Rafa=C3=ABl=20Carr=C3=A9?= Date: Wed, 3 Jun 2009 23:45:15 +0200 Subject: [PATCH] Move Sansa AMS timer code in the target tree --- firmware/target/arm/as3525/timer-as3525.c | 163 +++++++++++++++++++++++++++++ firmware/timer.c | 35 ------ 2 files changed, 163 insertions(+), 35 deletions(-) create mode 100644 firmware/target/arm/as3525/timer-as3525.c diff --git a/firmware/target/arm/as3525/timer-as3525.c b/firmware/target/arm/as3525/timer-as3525.c new file mode 100644 index 0000000..37d9935 --- /dev/null +++ b/firmware/target/arm/as3525/timer-as3525.c @@ -0,0 +1,163 @@ +/*************************************************************************** +* __________ __ ___. +* Open \______ \ ____ ____ | | _\_ |__ _______ ___ +* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / +* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < +* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ +* \/ \/ \/ \/ \/ +* $Id$ +* +* Copyright (C) 2008 Rafaël Carré +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation; either version 2 +* of the License, or (at your option) any later version. +* +* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY +* KIND, either express or implied. +* +****************************************************************************/ + +#include "as3525.h" +#include "timer.h" +#include "stdlib.h" + +void INT_TIMER1(void) +{ + if (pfn_timer != NULL) + pfn_timer(); + + TIMER1_INTCLR = 0; /* clear interrupt */ +} + +bool __timer_set(long cycles, bool start) +{ + if (start) + { + if (pfn_unregister != NULL) + { + pfn_unregister(); + pfn_unregister = NULL; + } + } + + TIMER1_LOAD = TIMER1_BGLOAD = cycles; + /* /!\ bit 4 (reserved) must not be modified + * periodic mode, interrupt enabled, no prescale, 32 bits counter */ + TIMER1_CONTROL = (TIMER1_CONTROL & (1<<4)) | + TIMER_ENABLE | + TIMER_PERIODIC | + TIMER_INT_ENABLE | + TIMER_32_BIT; + return true; +} + +bool __timer_register(void) +{ + CGU_PERI |= CGU_TIMER1_CLOCK_ENABLE; /* enable peripheral */ + VIC_INT_ENABLE |= INTERRUPT_TIMER1; + return true; +} + +void __timer_unregister(void) +{ + TIMER1_CONTROL &= 0x10; /* disable timer 1 (don't modify bit 4) */ + VIC_INT_EN_CLEAR = INTERRUPT_TIMER1; /* disable interrupt */ + CGU_PERI &= ~CGU_TIMER1_CLOCK_ENABLE; /* disable peripheral */ +} +iff --git a/firmware/timer.c b/firmware/timer.c +ndex e9f11b6..bcaacba 100644 +-- a/firmware/timer.c +++ b/firmware/timer.c +@ -61,14 +61,6 @@ void TIMER1(void) + pfn_timer(); + TER1 = 0xff; /* clear all events */ +} +#elif CONFIG_CPU == AS3525 +void INT_TIMER1(void) +{ + if (pfn_timer != NULL) + pfn_timer(); + + TIMER1_INTCLR = 0; /* clear interrupt */ +} +#elif defined(CPU_PP) +void TIMER2(void) +{ +@ -109,23 +101,17 @@ void TIMER1_ISR(void) + +static bool timer_set(long cycles, bool start) +{ +#if CONFIG_CPU == SH7034 || defined(CPU_COLDFIRE) || CONFIG_CPU == AS3525 +#if CONFIG_CPU == SH7034 || defined(CPU_COLDFIRE) + int phi = 0; /* bits for the prescaler */ + int prescale = 1; + +#if CONFIG_CPU == SH7034 || defined(CPU_COLDFIRE) +#define PRESCALE_STEP 1 +#else /* CONFIG_CPU == AS3525 */ +#define PRESCALE_STEP 4 +#endif + + while (cycles > 0x10000) + { /* work out the smallest prescaler that makes it fit */ +#if CONFIG_CPU == SH7034 || CONFIG_CPU == AS3525 +#if CONFIG_CPU == SH7034 + phi++; +#endif + prescale <<= PRESCALE_STEP; + cycles >>= PRESCALE_STEP; + prescale <<= 1; + cycles >>= 1; + } +#endif + +@ -177,25 +163,6 @@ static bool timer_set(long cycles, bool start) + and_b(~0x01, &TSR4); /* clear an eventual interrupt */ + + return true; +#elif CONFIG_CPU == AS3525 + /* XXX: 32 bits cycles could be used */ + if (prescale > 256 || cycles > 0x10000) + return false; + + if (start) + { + if (pfn_unregister != NULL) + { + pfn_unregister(); + pfn_unregister = NULL; + } + } + + TIMER1_LOAD = TIMER1_BGLOAD = cycles; + /* /!\ bit 4 (reserved) must not be modified + * periodic mode, interrupt enabled, 16 bits counter */ + TIMER1_CONTROL = (TIMER1_CONTROL & (1<<4)) | 0xe0 | (phi<<2); + return true; +#elif defined CPU_COLDFIRE + if (prescale > 4096/CPUFREQ_MAX_MULT) + return false; +@ -320,10 +287,6 @@ bool timer_register(int reg_prio, void (*unregister_callback)(void), + irq_set_int_handler(IRQ_TIMER1, TIMER1_ISR); + irq_enable_int(IRQ_TIMER1); + return true; +#elif CONFIG_CPU == AS3525 + CGU_PERI |= CGU_TIMER1_CLOCK_ENABLE; /* enable peripheral */ + VIC_INT_ENABLE |= INTERRUPT_TIMER1; + return true; +#else + return __TIMER_REGISTER(reg_prio, unregister_callback, cycles, + int_prio, timer_callback); +@ -357,10 +320,6 @@ void timer_unregister(void) +#elif CONFIG_CPU == PNX0101 + TIMER1.ctrl &= ~0x80; /* disable timer 1 */ + irq_disable_int(IRQ_TIMER1); +#elif CONFIG_CPU == AS3525 + TIMER1_CONTROL &= 0x10; /* disable timer 1 (don't modify bit 4) */ + VIC_INT_EN_CLEAR = INTERRUPT_TIMER1; /* disable interrupt */ + CGU_PERI &= ~CGU_TIMER1_CLOCK_ENABLE; /* disable peripheral */ +#else + __TIMER_UNREGISTER(); +#endif diff --git a/firmware/timer.c b/firmware/timer.c index 1cd913b..bcaacba 100644 --- a/firmware/timer.c +++ b/firmware/timer.c @@ -61,14 +61,6 @@ void TIMER1(void) pfn_timer(); TER1 = 0xff; /* clear all events */ } -#elif CONFIG_CPU == AS3525 -void INT_TIMER1(void) -{ - if (pfn_timer != NULL) - pfn_timer(); - - TIMER1_INTCLR = 0; /* clear interrupt */ -} #elif defined(CPU_PP) void TIMER2(void) { @@ -171,25 +163,6 @@ static bool timer_set(long cycles, bool start) and_b(~0x01, &TSR4); /* clear an eventual interrupt */ return true; -#elif CONFIG_CPU == AS3525 - if (start) - { - if (pfn_unregister != NULL) - { - pfn_unregister(); - pfn_unregister = NULL; - } - } - - TIMER1_LOAD = TIMER1_BGLOAD = cycles; - /* /!\ bit 4 (reserved) must not be modified - * periodic mode, interrupt enabled, no prescale, 32 bits counter */ - TIMER1_CONTROL = (TIMER1_CONTROL & (1<<4)) | - TIMER_ENABLE | - TIMER_PERIODIC | - TIMER_INT_ENABLE | - TIMER_32_BIT; - return true; #elif defined CPU_COLDFIRE if (prescale > 4096/CPUFREQ_MAX_MULT) return false; @@ -314,10 +287,6 @@ bool timer_register(int reg_prio, void (*unregister_callback)(void), irq_set_int_handler(IRQ_TIMER1, TIMER1_ISR); irq_enable_int(IRQ_TIMER1); return true; -#elif CONFIG_CPU == AS3525 - CGU_PERI |= CGU_TIMER1_CLOCK_ENABLE; /* enable peripheral */ - VIC_INT_ENABLE |= INTERRUPT_TIMER1; - return true; #else return __TIMER_REGISTER(reg_prio, unregister_callback, cycles, int_prio, timer_callback); @@ -351,10 +320,6 @@ void timer_unregister(void) #elif CONFIG_CPU == PNX0101 TIMER1.ctrl &= ~0x80; /* disable timer 1 */ irq_disable_int(IRQ_TIMER1); -#elif CONFIG_CPU == AS3525 - TIMER1_CONTROL &= 0x10; /* disable timer 1 (don't modify bit 4) */ - VIC_INT_EN_CLEAR = INTERRUPT_TIMER1; /* disable interrupt */ - CGU_PERI &= ~CGU_TIMER1_CLOCK_ENABLE; /* disable peripheral */ #else __TIMER_UNREGISTER(); #endif -- 1.6.0.4