Index: firmware/export/tcc77x.h
===================================================================
--- firmware/export/tcc77x.h	(revision 28569)
+++ firmware/export/tcc77x.h	(working copy)
@@ -21,6 +21,8 @@
 #ifndef __TCC77X_H__
 #define __TCC77X_H__
 
+#define CACHEALIGN_BITS (5)
+
 /* General-purpose IO */
 
 #define GPIOA      (*(volatile unsigned long *)0x80000300)
Index: firmware/export/system.h
===================================================================
--- firmware/export/system.h	(revision 28569)
+++ firmware/export/system.h	(working copy)
@@ -309,18 +309,21 @@
 }
 #endif
 
-#ifndef CACHEALIGN_SIZE /* could be elsewhere for a particular reason */
+/* Calculate CACHEALIGN_SIZE from CACHEALIGN_BITS */
+#ifdef CACHEALIGN_SIZE
+    /* undefine, if defined. always calculate from CACHEALIGN_BITS */
+    #undef CACHEALIGN_SIZE
+#endif
 #ifdef CACHEALIGN_BITS
-/* 2^CACHEALIGN_BITS = the byte size */
-#define CACHEALIGN_SIZE (1u << CACHEALIGN_BITS)
+    /* CACHEALIGN_BITS = 2 ^ CACHEALIGN_BITS */
+    #define CACHEALIGN_SIZE (1u << CACHEALIGN_BITS)
 #else
-#define CACHEALIGN_SIZE 16  /* FIXME */
+    /* FIXME: set to maximum known cache alignment of supported CPUs */
+    #define CACHEALIGN_BITS  5
+    #define CACHEALIGN_SIZE 32
 #endif
-#endif /* CACHEALIGN_SIZE */
 
-#ifdef PROC_NEEDS_CACHEALIGN
 /* Cache alignment attributes and sizes are enabled */
-
 #define CACHEALIGN_ATTR __attribute__((aligned(CACHEALIGN_SIZE)))
 /* Aligns x up to a CACHEALIGN_SIZE boundary */
 #define CACHEALIGN_UP(x) \
@@ -335,19 +338,6 @@
 #define CACHEALIGN_BUFFER(start, size) \
     ALIGN_BUFFER((start), (size), CACHEALIGN_SIZE)
 
-#else /* ndef PROC_NEEDS_CACHEALIGN */
-
-/* Cache alignment attributes and sizes are not enabled */
-#define CACHEALIGN_ATTR
-#define CACHEALIGN_AT_LEAST_ATTR(x) \
-    __attribute__((aligned(x)))
-#define CACHEALIGN_UP(x) (x)
-#define CACHEALIGN_DOWN(x) (x)
-/* Make no adjustments */
-#define CACHEALIGN_BUFFER(start, size)
-
-#endif /* PROC_NEEDS_CACHEALIGN */
-
 #ifdef STORAGE_WANTS_ALIGN
 #define STORAGE_ALIGN_ATTR __attribute__((aligned(CACHEALIGN_SIZE)))
 #define STORAGE_ALIGN_DOWN(x) \
Index: firmware/export/mcf5249.h
===================================================================
--- firmware/export/mcf5249.h	(revision 28569)
+++ firmware/export/mcf5249.h	(working copy)
@@ -21,6 +21,8 @@
 #ifndef __MCF5249_H__
 #define __MCF5249_H__
 
+#define CACHEALIGN_BITS (4)
+
 #define MBAR  0x40000000
 #define MBAR2 0x80000000
 
Index: firmware/export/as3525v2.h
===================================================================
--- firmware/export/as3525v2.h	(revision 28569)
+++ firmware/export/as3525v2.h	(working copy)
@@ -26,6 +26,8 @@
 
 /* insert differences here */
 
+#define CACHEALIGN_BITS (5)
+
 #ifndef IRAM_SIZE   /* protect in case the define name changes */
 #   error IRAM_SIZE not defined !
 #endif
Index: firmware/export/tcc780x.h
===================================================================
--- firmware/export/tcc780x.h	(revision 28569)
+++ firmware/export/tcc780x.h	(working copy)
@@ -21,6 +21,8 @@
 #ifndef __TCC780X_H__
 #define __TCC780X_H__
 
+#define CACHEALIGN_BITS (5)
+
 #define TTB_SIZE      (0x4000)
 /* must be 16Kb (0x4000) aligned */
 #define TTB_BASE_ADDR (0x20000000 + (MEMORYSIZE*1024*1024) - TTB_SIZE)
Index: firmware/export/imx31l.h
===================================================================
--- firmware/export/imx31l.h	(revision 28569)
+++ firmware/export/imx31l.h	(working copy)
@@ -38,7 +38,6 @@
 #define FRAME         ((void *)(FRAME_PHYS_ADDR+0x100000-CSD0_BASE_ADDR))
 
 #define CACHEALIGN_BITS     5
-#define CACHEALIGN_SIZE     32
 #define NOCACHE_BASE        CSD0_BASE_ADDR
 
 /* USBOTG */
Index: firmware/target/arm/system-target.h
===================================================================
--- firmware/target/arm/system-target.h	(revision 28569)
+++ firmware/target/arm/system-target.h	(working copy)
@@ -158,10 +158,6 @@
     ((typeof (a))((uintptr_t)(a) | UNCACHED_BASE_ADDR))
 #endif /* BOOTLOADER */
 
-/* Certain data needs to be out of the way of cache line interference
- * such as data for COP use or for use with UNCACHED_ADDR */
-#define PROC_NEEDS_CACHEALIGN
-
 #if defined(CPU_PP502x) && defined(HAVE_ATA_DMA)
 #define STORAGE_WANTS_ALIGN
 #endif