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Cowon D2 Info
Introduction
The Cowon D2 is a flash-based DAP/PMP with a 320x240 touchscreen, SD card slot, FM radio and TV-Out. It comes in 2GB, 4GB and 8GB sizes, and there is also a version with DAB digital radio.
Hardware
Port Status
A functioning bootloader and a work-in-progress main build have been committed to SVN. It is possible to boot the Rockbox menu and run various plugins. There is no touchscreen driver and only basic button mappings, so many plugins are unusable at this stage. Various demos (eg. fire, plasma, cube, star) and the Invadrox game are playable. There is currently no sound output.
By default, the bootloader build is configured to produce a bootloader.bin suitable for patching into a Cowon firmware using mktccboot. This mechanism is used to provide dual-boot functionality between the OF and Rockbox (immediately set the hold switch after power-on to boot Rockbox).
The port is expected to function on any D2 variant (2/4/8Gb, standard, DAB or DMB) although this is yet to be tested extensively.
NOTE: The current Rockbox build is not functional - it is not in any way a replacement for the Cowon firmware. The following installation instructions are intended for a developer/test audience only.
Steps to Install
You will need a copy of your current Cowon firmware, ie. the D2(N).bin file from the '1' folder in an official firmware update archive. Note that this file is named D2.bin for DAB/DMB players, otherwise D2N.bin.
1. Compile a (B)ootloader build (in a new folder eg. rockbox/d2_boot).
2. Patch the bootloader into the Cowon firmware using the following command: ../tools/mktccboot path_to_firmware/1/D2N.bin bootloader/bootloader.bin d2_patched.bin
3. Compile a (N)ormal build (use 'make' and then 'make zip', in a new folder eg. rockbox/d2_main).
4. Unzip the resulting rockbox.zip to the root of your player. (note: a pre-built "bleeding edge" zip can be found here).
The d2_patched.bin can then either be uploaded to the player using Tcctool (don't forget to set the hold switch, as this is a dual-boot image), or flashed to the player using the usual firmware upgrade method. To do this rename the file to D2.bin or D2N.bin as appropriate, copy it to the root of the player, then boot the OF.
It is also possible to 'preview' a (N)ormal Rockbox binary on the device, by using tcctool to upload the apps/rockbox.bin file (NOT rockbox.iaudio). Note that this is only suitable for minor development/testing purposes, since plugins/codecs are not updated when using this method.
Known Problems
- The ATA/NAND driver is not complete, and as such it is not 100% reliable. If the bootloader displays a "File Not Found" or "Bad Checksum" error, copy the rockbox.iaudio file a second (or third) time and try again until it works.
- The flash driver is read-only at present, so unexpected behaviour can occur if Rockbox or a plugin tries to write to the disk.
- Recent changes appear to have disabled the CPU cache in the bootloader, so the initial FAT mount takes longer than expected.
- Battery readings are not calibrated, and change significantly when a USB cable or AC adapter is connected. The estimated runtime should be ignored for the time being.
- The top 2-3 lines of the display are often missing and/or displayed at the bottom of the LCD. Potentially screen address alignment issue?
Forum thread
The New Ports forum thread for the D2 is at:
http://forums.rockbox.org/index.php?topic=10164.0
Firmware Upgrade
Firmware upgrades are in the standard Telechips "dual-crc" format (more info at TelechipsInfo). Firmware upgrade files (D2.bin or D2N.bin) are a raw, unencrypted dump of SDRAM (base address 0x20000000). This is loaded from flash during normal startup by an 8KB Boot ROM.
The device also has a USB boot mode, and can be accessed via the tcctool utility (in Rockbox SVN). USB boot mode is enabled by powering the unit off, then holding any of the keypad buttons ('-', 'M', or '+') while inserting the USB cable.
Note that the "dual-crc" format does not appear to be required when using USB boot mode.
Firmware Versions
There are several variants of the D2 retail firmware tailored for different markets and hardware versions. The variant is identified by the Major version number.
| Major version |
Hardware |
Features |
Default Language |
| 1.xx |
D2 DMB/DAB |
MSC, Flash skins, Dictionary |
Korean |
| 2.xx |
D2 |
MSC/MTP |
English |
| 3.xx |
D2 |
MSC, Flash skins, Dictionary |
Korean |
| 4.xx |
D2 DAB/DMB |
MSC/MTP |
English |
| 5.xx |
D2 TV (Japan) |
? |
? |
Firmware archives downloaded from Cowon are split into three subfolders, each containing one or more .bin files.
- "0" - Applying this D2.bin will perform a low-level format of the D2's internal flash. Use with care (and do not upload it with Tcctool!).
- "1" - D2.bin contains the main firmware image. You can "preview" different firmwares by uploading this file with Tcctool. This is the file that is patched by mktccboot.
- "2" - D2_rs.bin is some form of resource (graphics) archive. D2_font.bin contains the UI font. Both of these can be patched to provide different "themes", using utilities available at the iAudiophile.net forums.
Technical Information
The TCC7801 has significant similarities to earlier Telechips SoCs such as the 76x (for which a datasheet was posted to the rockbox-dev mailing list here). The following hardware registers appear to be the same as the 76x:
| Register Range |
76x base |
7801 base |
| Timers/Counters |
0x80000200 |
0xF3003000 |
| ADC Controller |
0x80000A00 |
0xF3004000 |
| Audio In/Out |
0x80000000 |
0xF0059000 |
| SDRAM Controller* |
0xF0000000 |
0xF1000000 |
(*the SDRAM controller appears to have a duplicate range at 0xF1001000, presumably for a second SDRAM bank?)
The IRQ/FIQ controller (base 0xF3001000) seems to be largely the same as the 76x (base 0x80000100) except there appears to be a priority mechanism whereby the IRQ number of the highest-priority IRQ occurring can be read from address 0xF3001080. 0xF3001044 bits 0,1 appear to be a master IRQ/FIQ enable flag.
IRQ numbers do not appear to be the same as 76x, although Cowon helpfully left quite a lot of debug text in their firmware (eg. search for '_HISR') which should help identify some of these.
GPIO ports
GPIO ports can be accessed as follows:
0xF005A0x0 = current value of GPIOx
0xF005A0x4 = direction for each pin (set = output, clear = input)
0xF005A0x8 = bits to set
0xF005A0xC = bits to clear
For example, the hold switch state is available by reading bit 3 of 0xF005A020. To enable the LCD backlight, write bit 6 to 0xF005A028.
GPIOA (base = 0xF005A020)
| A0 |
out |
I2C SCL |
PCF50606 and WM8985 on this I2C bus, amongst others. |
| A1 |
in/out |
I2C SDI |
| A2 |
in |
~ON_OFF |
cleared when On/Off pressed |
| A3 |
in |
~HOLD |
cleared when Hold switch enabled |
| A6 |
out |
|
LCD backlight enable |
| A16 |
out |
|
LCD panel power (?) |
| A24 |
out |
LCD_CS |
| A25 |
out |
LCD_SCL |
see LCD panel datasheet |
| A26 |
in/out |
LCD_SDI |
GPIOB (base = 0xF005A040)
| B2 |
in |
|
set on keypad press (-, M, +) |
| B26 |
in |
~SDMMC |
SD/MMC present (active low) |
| B29 |
in |
~PCFINT |
PCF50606 interrupt (active low) |
GPIOC (base = 0xF005A060)
| C26 |
in |
Battery Charging? (active low) |
GPIOD (base = 0xF005A080)
| D23 |
in |
AC Charger Connected? |
GPIOE (base = 0xF005A0A0)
| Unknown (always 0x0FFFFFFF) |
Notes:
- When USB is connected, C26 goes low.
- When AC Adapter is connected and powered, C26 goes low and D23 goes high.
ADCs
- ADC0 provides an indication of the keypad state for the '-', 'M' and '+' buttons.
- ADC1 appears to provide an indication of current battery voltage (note that the actual voltage can be read from the PCF50606 chip).
- ADCs 2-3 are unknown (both appear to fluctuate with a wide range of values).
LCD
The LCD is powered on and off using the sequences given in the LTV250QV datasheet. The LCD is not visible at all unless the backlight is enabled, so it is necessary to first set the backlight intensity using PCF50606 register 0x35 and then enable it using GPIOA6.
Hardware registers for the LCD controller are TBC (base = 0xF0000000), however a working initialisation sequence has been identified from the OF.
NAND flash
The following D2's have been observed:
- 2Gb : 1x SAMSUNG K9LAG08U0M (2048+64 bytes page size)
- 4Gb : 2x SAMSUNG K9LAG08U0M ""
- 8Gb : 2x SAMSUNG K9LBG08U0M (4096+128 bytes page size)
See TelechipsNAND for further information.
Audio
The WM8985 is powered by the PCF50606 regulator D3REG. In the original firmware this is configured for 3.3v output by sending 0xF8 to D3REGC1 (0x26).
Using the recommended i2c start-up sequence from the WM8985 datasheet, it is possible to turn on the headphone output and control the volume (noise can be heard through the headphone output). Rough attempts to send audio data to the device haven't been successful yet.
Power management
The original firmware sends a number of initialisation commands to the PCF50606 to control the voltages that go to the various chips in the D2. It would be helpful to work out which regulator outputs each chip is connected to.
| Register |
Address |
Value |
Purpose |
Application |
| DCDEC1 |
0x1F |
0xE4 |
2.1v output |
|
| DCUDC1 |
0x21 |
0xE7 |
3.0v output |
|
| IOREGC |
0x23 |
0xF5 |
3.0v output |
|
| D1REGC1 |
0x24 |
0xF5 |
3.0v output |
|
| D2REGC1 |
0x25 |
0xE9 |
1.8v output |
|
| D3REGC1 |
0x26 |
0xF8 |
3.3v output |
WM8985 AVDD1,AVDD2,DBVDD |
| LPREGC1 |
0x27 |
0x00 |
0.9v output |
|
| LPREGC2 |
0x28 |
0x02 |
LPREG off in standby, reset in standby |
|
| PWMC1 |
0x35 |
0xE9 |
PWM freq/duty cycle |
LCD backlight |
| GPOC1 |
0x38 |
0x03 |
Configure GPO0 for PWM output |
LCD backlight |
CategoryFrontpage: Cowon D2 Port Index [New Ports]
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Copyright © 1999-2008 by the contributing authors.
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