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Wiki > Main > GigabeatFXPort > GigabeatInfo > GigabeatPortPins

Gigabeat Port Pin Assignments

The values of the port pin control registers after boot:

Port Config value
A 00 FF FF FF
B 00 01 54 95
C AA A0 54 A8
D AA A0 AA A5
E AA 80 02 AA
F 00 00 0A AA
G 01 50 10 00
H 00 15 40 A5

Port A

Port pin I/O/F Description CPU pin
0 F ADDR0 F7
1 F ADDR16 D9
2 F ADDR17 G9
3 F ADDR18 F9
4 F ADDR19 H9
5 F ADDR20 D10
6 F ADDR21 C10
7 F ADDR22 H10
8 F ADDR23 E10
9 F ADDR24 C11
10 F ADDR25 D10
11 F ADDR26 G11
12 F nGCS[1] B2
13 F nGCS[2] C3
14 F nGCS[3] C4
15 F nGCS[4] D3
16 F nGCS[5] C2
17 F CLE F5
18 F ALE D1
19 F nFWE F3
20 F nFRE E1
21 F nRSTOUT N13
22 F nFCE F4

Port B

Port pin I/O/F Description CPU pin
0 O   J6
1 O   J5
2 O SC606 enable J7
3 F TOUT3 to generate audio beeps K3
4 I/O USB2ATA: RESET# K4
5 O USB2ATA: ATA_EN K2
6 O USB2ATA: VBUS_PRW_VALID L5
7 O LCD reset K7
8 O LCD CS K5
9 I   L3
10 I   K6

Port C

Port pin I/O/F Description CPU pin
0 I flash related L1
1 F VCLK M4
2 F VLINE M1
3 F VFRAME L7
4 I flash related M4
5 O mutes headphone output (HPDETECT?) M3
6 O flash lock M2
7 O SDI/SDO to DAC switch P1
8 I flash related N2
9 I flash related L6
10 F video data B0 N4
11 F video data B1 R1
12 F video data B2 N3
13 F video data B3 P2
14 F video data B4 M6
15 F video data B5 P3

Port D

Port pin I/O/F Description CPU pin
0 O cradle: speaker amp control? R2
1 O cradle: speaker amp control? N5
2 F video data G0 M5
3 F video data G1 R3
4 F video data G2 P4
5 F video data G3 R4
6 F video data G4 P5
7 F video data G5 N6
8 I   M7
9 I   T4
10 F video data R0 R5
11 F video data R1 T5
12 F video data R2 P6
13 F video data R3 R6
14 F video data R4 N7
15 F video data R5 U5

Port E

Port pin I/O/F Description CPU pin
0 F I2SLRCK P7
1 F I2SSCLK R7
2 F CDCLK T7
3 F I2SDI L8
4 F I2SDO U6
5 I   N8
6 I   K8
7 I   R8
8 I   M8
9 I   P8
10 I   J9
11 F SPIMOSO0 K9
12 F SPIMOSI0 P9
13 F SPICLK0 L9
14 F IICSCL U8
15 F IICSDA M9

Port F

Port pin I/O/F Description CPU pin
0 F EINT0 / unit USB connected N17
1 F EINT1 / cradle USB connected M16
2 F EINT2 / ATA IRQ L13
3 F EINT3 M15
4 F EINT4 / charger connected (main or cradle) M17
5 F EINT5 L14
6 F EINT6 / cradle sync button L15
7 I cradle CD rip button L16

Port G

Port pin I/O/F Description CPU pin
0 I power button N9
1 I menu button T9
2 I volume up button J10
3 I volume down button R10
4 I A button P11
5 I   K11
6 O RI Onkyo? (set to 0 in legna_misc_cradle_power_on) R10
7 I   L10
8 I battery charging T10
9 I battery switch M11
10 O USB2ATA: ARESET# N10
11 O set to 1 in power_up_seq in hdd_pm, 0 spins down drive, 1 spins up drive U12
12 O set to 0 in power_up_seq in hdd_pm M10
13 I cradle powered T11
14 I cradle usb/line-in switch L11
15 I hold switch U13

Port H

Port pin I/O/F Description CPU pin
0 O   K11
1 O   L17
2 F TXD0 K13
3 F RXD0 K14
4 I   K16
5 I   K17
6 I   J11
7 O Dock connector bus switch enable J15
8 O Cradle power control K15
9 I/O SC606 serial data R9
10 O SC606 serial clock P10

Port J (touchpad)

Port pin I/O/F Description CPU pin
0 I up++ H6
1 I up+ G3
2 I up H5
3 I center H4
4 I down H3
5 I down+ H7
6 I down++ J8
7 I left++ H2
8 I left+ G5
9 I left G7
10 I right G2
11 I right+ J3
12 I right++ J4

Dock connector

40_pin_connector.JPG

Port pin Description Name on block diagram
1 ground
2 data – (USB2ATA) USB 2.0 Hi-Speed
3 data + (USB2ATA)
4 ground  
5 line-out R Lineout
6 line-out L
7 ground  
8 IICCLK * I2C
9 IICSDA *
10 I2SLRCK * I2S LRCK
11 I2SSCLK * I2S SCLK
12 I2SSDI * I2S SDI
13 I2SSDO * I2S SDO
14 GPC7: SDI/SDO to DAC switch * I2SMASTER (GPIO)
15 GPD1 Speaker amp control
16 GPD0
17 GPG13 Optiondetect
18 GPG6 (via resistor R127) RI Onkyo I/F
19 VSSiarm??
20 GPG14: cradle usb/line-in switch Slide switch x 1 (GPIO)
21 GPF6 & ADC input 2 (3rd) - sync button Cradle button x 2 (GPIO&ADC)
22 GPF7 & ADC input 3 (4th) - CD rip button
23 data – for usb peripheral USB 1.1 device
24 data + for usb peripheral
25 data – from usb host USB 1.1 host [0]
26 data + from usb host
27 GPH8: cradle power control Maindetect (GPIO)
28 GPF1: cradle USB connected Cradle-usb5Vdetect (GPIO)
29 DP5: +5V P5.0V from cradle
30
31
32
33 NC  
34 DP23: PVOUT +4.2V to cradle
35
36 ground from cradle  
37 ground  
38
39
40

* these pins can be enabled/disabled with H8

Debug connector

Port pin Description
1 ground
2 nTRST
3 GPH3: RXD0
4 +
5 nRESET
6 TCK
7 TDO
8 TMS
9 GPH2: TXD0
10 TDI

r38 - 02 Apr 2021 - 20:46:06 - UnknownUser

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