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Wiki > Main > SummerOfCode > SummerOfCode2009 > GSoCSansaView (r11)

Page heading

Rockbox on the Sansa View

This project is part of the Google Summer of Code 2009 project.

Project name Student Mentor Backup mentor
Port of Rockbox to the Sansa View Robert Keevil Paul Louden Daniel Stenberg

The aim of this project is to

Project Plan

  • Disassembly of the Views OF.
  • LCD Driver
  • Button Driver
  • Flash Driver
  • Audio Driver

Currently working on:

  • Disassembly!
  • Many registers seem to match PP502x ones. This includes Mailboxes, Interrupts, Timers, Processor Control, Cache Control and GPIOs.
  • The registers for LCD and MMC/IO are different to earlier Portal Player implementations
  • Locate OF hardware initialisation routines

Dissassembly

For the disassembly I arbitrarily chose the 01.01.06a revision of the OF to work on, which is available at http://daniel.haxx.se/sansa/view.html. Before disassembling the bootloader, I stripped the first 64 bytes, which contain header information. Thanks to funman for pointing out to me that infact there isn't a 64 byte header (why I thought that I don't know), and also for the RAM insights below. Re-disassembled with the correct file (TODO: update offsets below). Both the bootloader and main OF binary are mixed thumb and 32bit ARM code.

IRAM is located at 0x40000000. There appears to be at least 96k worth? The OF maps the RAM to 0x10F00000. The bootloader appears to be copied to the start of this address, and then uses this offset to call various bits of code when running.

The code is a little generic? It tests if a COP is present, and also tries to setup 64Mb of RAM, even though the View has 32 (as indicated by the part number on the Samsung chip).

Offset Function Notes
0x29FC COP Test - if true, initialise COP_CTL Nvidias own 6100 webpage implies single core, with a secondary Audio/Video processor?
0x3354 udelay(r0)  
0x5248 USB init See also 0x5352 & 0x53A4. Seems to be using the same registers and values as previous PP502Xs.
0x5CC8 lcd_init_gpio GPIO initialisation - E, F, J, B, H and more
0x623C GPIOB See also 0xC350 and 0xBB74
0x6278 lcd_write_reg  
0x643C backlight_on/_off(r1) set r1 to 0 to turn off, otherwise on
0x645C lcd_send_msg  
0x6478 lcd_send_byte  
0xBE28 GPIO H, I and O initialisation The 6100 seems to have 4 more GPIOs than the PP502Xs

Experimentation

I've also been experimenting with code hoping to find some clues I can use as references when looking at the disassembly, by using code like:

for (i = 0; i <= 31; i++)
{
    GPIO_CLEAR_BITWISE(GPIOB_OUTPUT_VAL, 1<<i);
    sleep(HZ/4);
}

within bootloader/main-pp.c, and then running it as a replacement to the OF (although a lot of the HW initialisation will already be done by that point?).

    GPIO_SET_BITWISE(GPIOB_OUTPUT_VAL, 1<<10);
makes the entire LCD white

    GPIO_SET_BITWISE(GPIOD_OUTPUT_VAL, 1<<8);
appears to turn off the LCD (i.e. it seems to be more than just turning the backlight off).

    GPIO_CLEAR_BITWISE(GPIOA_ENABLE, 0x2);
Turns ON the button light

    GPIO_SET_BITWISE(GPIOA_ENABLE, 0x2);
Turns off the button light

    /* Disable interrupts on this core */
    disable_interrupt(IRQ_FIQ_STATUS);

    /* Mask them on both cores */
    CPU_INT_DIS = -1;

    while (1)
    {
        DEV_RS = -1;
        CPU_CTL = 0x40000000;
    }
This is an amalgam of other PP targets shutdown code - on the View it actually resets the device (useful since I can use it to let me know when certain code/sleeps have finished). TODO: find the real reboot/shutdown code.

void bl_off(void)
{
    GPIO_SET_BITWISE(GPIOD_ENABLE, 1<<8);
}

void bl_on(void)
{
    GPIO_SET_BITWISE(GPIOD_ENABLE, 1);
}
Turn the backlight on and off.

    GPIO_CLEAR_BITWISE(GPIOJ_OUTPUT_EN, 0x2);
    GPIO_CLEAR_BITWISE(GPIOJ_ENABLE, 0x2);
The first line corrupts the display (skews it). The second restores it to normal.

LCD

At first I thought the LCD was based on a Renesas controller, since the disassembly looked similar to the e200. This unfortunately turned out to be a massive red herring. Infact the controller appears to be an Ilitek ILI9320 (although this model is very nearly identical register-wise to the Renesas R61505).

So far I'm using the values from the disassembly in the LCD init routines, rather than the application notes. Despite this wealth of information I've yet to have any success in writing to the display.

The exact same functions/layout are in both the bootloader and main firmware images:

Boot Index: 0x62818 OF Index: 0x321DBC

The function name refers to lcd-view.c

Index Boot Offset OF Offset function Notes
0x00 0x5CC8 0x88284 lcd_init_gpio This touches a lot of GPIOs - all really LCD related?
0x04 0x643C 0x88E70 N/A backlight(bool r0)
0x08 0x6308 0x88D0C unknown02 screen power off/sleep ?
0x0C 0x62C4 0x88CA0 unknown01 screen power on/wake ?
0x10 0x623C 0x88BDC unknown04  
0x14 0x6410 0x88E30 unknown03  
0x18 0x63B8 0x88E28 N/A r0=0x12
0x1C 0x63B4 0x88E20 N/A r0=0x3C
0x20 0x633C 0x88D5C lcd_power_on  
0x24 0x645C 0x88E90 lcd_send_msg  
0x28 0x6278 0x88C2C lcd_write_reg  
0x2C 0x62B8 0x88C88 N/A r0=0xF0 // LCD_WIDTH
0x30 0x62B0 0x88C80 N/A r0=0x140 // LCD_HEIGHT
0x34 0x6300 0x88CFC N/A r0=0x4
0x38 0x62FC 0x88CF4 N/A r0=0x4
0x3C 0x6338 0x88D54 N/A r0=0x0
0x40 0x62BE 0x88C98 N/A r0=0x1
0x44 0x62BB 0x88C90 N/A r0=0x3
0x48 0x6304 0x88D04 N/A r0=0x5

Notes

There are many references in the main OF binary to OpenMAX. Khronos were mentioned as the developer of a reference design when the Nvidia 6100 SOC was launched.

I've sent emails to both Nvidia and Dragon Display Tech requesting technical information/data sheets. No response has so far been received.
I Attachment Action Size Date Who Comment
ILI9320AN_V0.92.pdfpdf ILI9320AN_V0.92.pdf manage 294.2 K 09 Jul 2009 - 21:22 RobertKeevil ILI9320 Application Notes
ILI9320DS_V0.55.pdfpdf ILI9320DS_V0.55.pdf manage 1210.2 K 09 Jul 2009 - 21:21 RobertKeevil ILI9320 Datasheet
backlight-view.cc backlight-view.c manage 1.4 K 09 Jul 2009 - 21:23 RobertKeevil  
lcd-view.cc lcd-view.c manage 9.7 K 10 Jul 2009 - 15:15 RobertKeevil  
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r11 - 17 Jul 2009 - 02:16:45 - RobertKeevil
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