BDM interface construction
Who is working on the BDM?
The Rockbox project has bought a http://www.pemicro.com/products/product_view.cfm?product_ID=105&menu_id=details P&E Wiggler
, and LinusNielsenFeltzing
will connect to the H-100 ASAP.
Documentation on the wiggler in Microsoft Word format: P&E BDM connection
The BDM interface is working!!!
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This GDB was configured as "--host=i686-pc-linux-gnu --target=m68k-bdm-elf".
(gdb) target bdm /dev/bdmcf3
CPU type: 1
Interface type: 1
Driver version: 2.c
CPU type: 1
Write system register TDR: 0x40000000
Read system register CSR: 0x1000000
Read system register RPC: 0x1260
Read system register VBR: 0x358
Read system register MBAR: 0x40000000
Detected V2 core
Set delay 0
GDB target bdm connected to /dev/bdmcf3
Coldfire debug module version is 0 (5206(e)/5272/5282)
: Am I right in thinking the coldfire bdm support in gdb does not actually support the registers of the 5249 (MBAR2, RAMBAR2, ...)? I guess those are not so important but that's something else that probably needs addressing at some point (and giving back to the community)
: Correct. It doesn't have support for the 5249 control registers. Some day, I might send them a patch...
A list of connector points on the H1xx to connect the BDM interface. The needed pins can be found in the MFC5249 Evaluation Board Schematics
| Connector Name
|| is connected PIN to
|| Break Point
|| Development Serial Clock
|| Reset Pin
|| Development Serial Input
|| Development Serial Output
|| Processor Status
|| Debug Data
|| 17 (not necessary)
|| 19 (not necessary)
|| Processor Clock
|| Core Voltage
|| Transfer Acknowledge
Clarification regarding the TEA/TA signal
The TEA signal in the BDM connector is used for terminating a hung bus access, i.e a bus error. The 68xxx family has a TEA signal to terminate a bus cycle when TA isn't asserted by the Chip Select logic. This generates a Bus Error on the 68xxx family. However, the 5249 doesn't have a TEA signal. Instead, the watchdog timer (SWT) takes care of the bus termination by asserting TA if the software doesn't respond to the IACK cycle of the watchdog timer interrupt.
The debugger has to be able to terminate a hung bus cycle. It does so by asserting the TEA/TA signal, which generates a bus error on the 68xxx and terminates the bus cycle normally on the 5249.
: P&E Wiggler Pinout (which also corresponds to the Motorola recommended BDM pinout in the User's Manual
Debugging with BDM/GDB
This is not exactly for the MFC5249, but it may still help:
http://www.ucdot.org/article.pl?sid=03/07/01/0630204&mode=thread Using gdb/bdm for hardware testing a 5272 board
MCF5206e BDM design: http://www.fortunecity.com/campus/psychology/493/bdm/bdm.htm
(broken link, http://www.google.com/search?q=cache:kGsTXTv_mKYJ:www.fortunecity.com/campus/psychology/493/bdm/bdm.htm+High-Speed+BDM+Pod+for+ColdFire+CPU Google cache
is still available)
This "article" is based on this BDM design which seems like a good design for fast-speed BDM:
Chip used in this design is a 20-pin PALCE16V8-25LNC
Flash Erasable, Reprogrammable CMOS PAL Device. Can anyone confirm if it will work for the Coldfire 5249?
The old Pisa BDM for m683xx
: (will not work on the Coldfire, but contains interesting info anyway)
Addtional BDM info:
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