release
dev builds
extras
themes manual
wiki
device status forums
mailing lists
IRC bugs
patches
dev guide



Search | Go
Wiki > Main > DocsIndex > RockChip (r10)


Introduction

Quoting wikipedia: "Rockchip is a series of integrated circuits manufactured by Fuzhou Rockchip Electronics Company. These integrated circuits are mainly for applications in mobile entertainment devices such as MP3 players and personal video players."


rk260x series

This SoC is build around ZSP400 type 16/32-bit DSP clocked up to 80MHz and as such is not suitable target for rockbox. Some documents leaked to internet as well as more or less complete SDK.


rk270x series

This SoC is build around ARM7EJ?-S (ARMv5TE? architecture) core with additional ZSP500 DSP coprocessor. There are some preliminary datasheets floating in internet as well as more or less complete SDK for the rockchip firmware. There is no free toolchain for ZSP architecture as far as I know.

A port exists to the official rockchip reference design: see: Rockchip27xxPort

Main prameters of the SoC are as follows:
  • ARM7EJS? (ARMv5TE? architecture) main core max. 200MHz (240MHz for rk2705)
  • ZSP500 DSP core max. 160MHz (176MHz for rk2705)
  • 8kB bootrom
  • 8kB (16kB ???) iram
  • Cache controller (2-way, 8-word cacheline size)
  • SDRAM controller
  • NAND flash controller (2705 seems to be 2706 with updated flash controller to accept flash chips from Intel and Hynix)
  • SD card controller
  • LCD controller
  • 3MPix Sensor for digital camera (optional)
  • DMA controllers
  • USB 2.0 host and device controllers (share the same PHY so only one at a time)
  • SPI
  • UART 1655
  • I2C? controller
  • I2S? controller
  • 3 32-bit timers
  • 4-channel PWM
  • Watchdog module
  • RTC module
  • 4-channel ADC converter
  • CODEC (24bit delta-sigma DAC + 16bit sigma-delta ADC) I2S? interface
  • 48 GPIO pins with interrupt capability

The ZSP500 is successor of ZSP400. Very little technical documents are available about this core. It is referred as G2 ISA and uses mix of 16 and 32bit width opcodes. G2 ISA is binary incompatible with G1 (ZSP400 and earlier). The DSP has separate data memory and instruction memory. Both regions are mapped in ARM core address space also, so data can be shared.

rk280x series

This SoC from 2009 is build around ARM926EJ?-S core with additional DSP core (ZSP800 probably). Some technical materials leaked to internet. The max frequency is between 350-600 MHz for ARM and 400-550 MHz for DSP (there is big discrepancy in various materials about this chip). It is quite widespread in cheap tablets running android.


rk281x

This is upgrade of the rk280x architecture and introduce GPU to support 3d rendering. Frequency limits are higher as well.

rk290x

The Rockchip 29xx, presented for the first time at CES 2011, is a Cortex A8 CPU and can run up to 1.2 Ghz.

rk291x

This is high performance SoC based on Cortex A8 core with one NEON coprocessor (around 1GHz upper freq limit). It integrates GPU 2D/3D fully compatible with OpenGL? ES2.0, ES1.1 and OpenVG? standards, hardware video decoder (H264, H263, RMVB, MPEG2, MPEG4, VC1, AVS, VP8), hardware video encodec for H264, hardware accelerators (encoder/decoder) for JPEG. Other then this the chip integrates common set of peripherals such as nand, sd, ddr ram, i2s, i2c, uart, spi, usb otg, rtc, pwm, adc, lcdc.

rknano-b

This Rockchip chip seems to be a stripped down version of the rk27xx which has an ARM core at 120MHz, has nand, usb slave, mmc/sd support and has an embedded pmu and audio codec. This chip explicitely targets mp3 players but little is know about it since no datasheet has leaked.
Edit | Attach | Print version | History: r16 | r11 < r10 < r9 < r8 | Backlinks | View wiki text | More topic actions...
r10 - 13 May 2012 - 16:09:29 - MarcinBukat

Parents: DocsIndex
Copyright by the contributing authors.