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Wiki > Main > ArchosOndio (compare)

Difference: ArchosOndio (r61 vs. r60)

Archos Ondio (the smallest Rockbox hardware)

About the box

The Ondio is Archos' flash player. No harddisk, 128 MB of internal flash, expandable by plugging a MultiMediaCard (MMC). It is based on the same SH platform as the Jukebox Player/Recorder models, so we've been able to adapt Rockbox to it.

For details, see the Ondio User Manual

There are two different models of the Ondio: The Ondio 128 FM Recorder, featuring a FM radio, and being able to record from that as well as from a built-in microphone and a line input, and the Ondio 128 SP, which does neither have recording nor a radio.

  • So small, but already running Rockbox:
    comparison.jpg

Status of the rockbox port / How you can help

  • All meaningful Rockbox features are supported.
  • Full hotswap support for MMC. Swapping MMCs on the fly is both supported in USB mode and in rockbox itself.
  • Multivolume support in rockbox. A unix-like approach allows simultaneous access to the internal flash and an MMC, using the internal flash as the root file system and mounting MMCs under /<MMC1>
  • All reasonable plugins are adapted, calendar and clock are missing because the Ondio has no RTC (real time clock).

So what could you do to help us? We are still interested in some information about different Ondio hardware versions. You could do the following:

  • Install a current daily build of rockbox on your Ondio
  • Disconnect USB and start using rockbox.
  • In case you discover any bugs, please report them; preferably using the patch tracker
  • Does your Ondio have a display backlight?? If yes, please report that, preferably with the exact model name and a photo. We did not find any Ondio that actually has a factory-installed backlight so far, in spite of being prepared on all PCBs we've seen.

View Inside

Front of PCB, with LCD in place
Ondio FMR. This had the LCD glued on top of the CPU Ondio SP. This didn't have the LCD glued Ondio FMR, old pcb version. LCD not glued
pcb_front.jpgpcb_front_sp.jpgpcb_front_v2B17.jpg
Front of PCB, with LCD bent away
Ondio FMR Ondio SP. Note the sheet of plastic serving as
a "spring" to push the display towards the case
Ondio FMR, old pcb. There is a shielding case underneath the white plastic.
pcb_front_lcd_off.jpgpcd_front_lcd_off_sp.jpgpcb_front_lcd_off_v2B17.jpg
Back of PCB (tuner daughterboard covering the USB bridge)
Ondio FMR Ondio SP. The tuner board is almost empty. Ondio FMR, old pcb-version.
pcb_back.jpgpcb_back_sp.jpgpcb_back_v2B17.jpg

Back without tuner and LCD:
pcb_back_tuner_off.jpg

New components

Chipfunctionold FMRFMRSPdatasheet
74AC08 quad AND gate   X X from Fairchild
74AC32 quad OR gate X     from Fairchild
NC7S08? single gate AND ? X X from Fairchild

Some components already moved to the DataSheets page.

Button layout and hookup

The Ondio has less keys: only the 4 direction keys, a combined On/Off button, and one menu key. "Hidden" buttons are a MMC card present switch and the USB detection. See KeymapOndio for how they are used in the Rockbox applications. The assignment to the analog ports and the values are different, so it needs an adjusted driver. Direction keys are all on AN4, giving various reading depending on which key is pressed. MMC, USB, Menu and On/Off are "digitally" connected to AN0, AN1, AN2 and AN3, respectively.

The ranges represent the readings from 1 Ondio FMR and 1 Ondio SP

  no card MMC inserted
Port AN0 value 3FF 001
  no USB USB plugged
Port AN1 value 3FF 003
  no key Menu
Port AN2 value 001 3FF
  no key On/Off
Port AN3 value 240..27C 003
  no key Up Down Left Right
Port AN4 value 001 1EC..1FB 142..14E 338..353 292..2A7

Port pin assignment

Many pins have the same mapping as our "classic" FM JBR, the one most similar to the Ondio.

Port pinCPU functionOndio usageremarkJBR FM
PA0 /CS4 MAS Parallel Port (for recording)   same
PA1 /RAS Out DRAM control   same
PA2 GP Out FM tuner power (low active) just prepared, transistor is missing new
PA3 GP Out Card detect (low active) to USB bridge, pin18 new
PA4 /WR Out Bus write signal   same
PA5 GP Out USB Enable (1=enable)   was PA10
PA6 /RD Out Bus read signal   same
PA7 GP Out internal MMC flash reset low active new
PA8 GP Out MAS POR Reset, low active directly connected to MAS Pin 9 same
PA9 GP Out MMC chip select   new
PA10 GP Out internal flash chip select unconfirmed (BGA) new
PA11 GP Out MAS PR DMA Request   same
PA12 GP Out enable internal MMC clock (polarity varies) to AC08/AC32, pin 5 new
PA13 /IRQ1 ready/busy from internal flash unconfirmed (BGA), also via resistor to MMC pin 9 new
PA14 GP Out backlight provision goes to empty footprint below CPU new
PA15 /IRQ3 MAS Demand IRQ, start demand inverted from MAS pin 29 same
         
PB0 GP Out LCD Serial Data to FM board, too, (n.c.with Philips tuner) same
PB1 GP Out LCD Serial Clock / FM Radio Serial Clock to FM I2C? clk same
PB2 GP Out LCD Data Select (1=data)   same
PB3 GP Out LCD Chip Select (0=active) / FM Radio BUSENABLE (1 = active)   same
PB4 GP I/O FM Radio I2C? Data   almost
PB5 GP Out Main power control (0=shut off)   same
PB6 GP Out I2C? Clock   was PB13
PB7 GP I/O I2C? Data   same
PB8 GP Out MAS SIBI to MAS pin 51, purpose unknown? new
PB9 TxD0 MAS Serial link for MP3 data   same
PB10 RxD1 SPI data read from MMC   new
PB11 TxD1 SPI data write to MMC   new
PB12 SCK0 MAS Serial Clock for MP3 data   same
PB13 SCK1 SPI clock to MMC   new
PB14 /IRQ6 MAS Demand IRQ, stop demand   same
PB15 GP In MAS PRTW input (0=ready)   same
         
PC0 AN0 MMC presence switch   new
PC1 AN1 USB detection   same
PC2 AN2 Menu button   was OFF
PC3 AN3 On/Off button   was ON
PC4 AN4 direction keys   similar
PC5 AN5 USB bridge activity to bridge, pin 27 new
PC6 AN6 Power good to SP6201, pin 4 new
PC7 AN7 Battery voltage 4.890 volt reads as 0x3FE was AN6

The MMC clock circuit (74AC08 / 74AC32)

Three of the gates are used as a little logic to enable/disable the clock for internal and external MMC. One gate is used as a buffer for USB mode enable.

New version: 74AC08, quad AND gate

comment connection pin   pin connection comment
  flash clock O2 8   7 Gnd Gnd  
connected to pin 6   A2 9   6 O1   connected to pin 9
connected to pin 12 MMC clock from bridge, Pin 20 B2 10   5 B1 PA12 measured 1 for internal, 0 for external MMC
  MMC clock O3 11   4 A1 SCK1 connected to pin 13
connected to pin 10 MMC clock from bridge, Pin 20 A3 12   3 O0 to NC7S08? pin 2 bridge clock enable
connected to pin 4 SCK1 B3 13   2 B0 PA5 USB enable (high active)
  Vcc Vcc 14   1 A0 PA5 USB enable (high active)

Measured signals at above chip for different mode of operation:

Signalnormal, internal cardnormal, external cardUSB, internal cardUSB, external card
PA5 0 0 1 1
SCK1 low pulses low pulses 1 1
PA12 1 1 (!) 1 0
Flash clock low pulses low pulses clock 0
Bridge clock 1 1 clock clock
MMC clock low pulses low pulses clock clock

Old version: 74AC32, quad OR gate

comment connection pin   pin connection comment
  flash clock O2 8   7 Gnd Gnd  
connected to pin 6   A2 9   6 O1   connected to pin 9
connected to pin 13 MMC clock from bridge, Pin 20 B2 10   5 B1 PA12 Internal MMC clock enable
  MMC clock O3 11   4 A1 SCK1 connected to pin 12
connected to pin 4 MMC clock from bridge, Pin 20 A3 12   3 O0 to NC7S08? pin 2 bridge clock enable
connected to pin 10 SCK1 B3 13   2 B0 PA5 USB enable (high active)
  Vcc Vcc 14   1 A0 PA5 USB enable (high active)

Measured signals at above chip for different mode of operation:

Signalnormal, internal cardnormal, external cardUSB, internal cardUSB, external card
PA5 0 0 1 1
SCK1 low pulses low pulses 0 0
PA12 0 0 (!) 0 1
Flash clock low pulses low pulses clock 1
Bridge clock 0 0 clock clock
MMC clock low pulses low pulses clock clock
  • The SCK bursts generated by the SH have a frequency of 1.5 MHz.
  • The clock generated by the bridge has a frequency of 12 MHz.

Tuner board connector

The tuner daughterboard is connected with two headers (firmly soldered, not pluggable). The 2-pin one is for power. Its Vcc is prepared to be switched via PA2, but the power transistor is missing on my board. Instead, it is bridged via a zero ohm resistor to general Vcc (always on). Perhaps this saved a few cents or tuner standby power is neglible.

The 10-pin header has the following pinout (viewed on top of tuner board, pin 1 is marked with a square pad):

comment connection pin   pin connection comment
  Phone right 2   1 Phone left  
  Tuner left 4   3 Tuner right  
PB1 I2C? clock 6   5 BUSENABLE PB3
PB4 I2C? data 8   7 n.c. PB0
  ON switch 10   9 Gnd  

HW mask bits and their meanings

The hardware mask consists of 2 bytes, but the second byte seems to be unused. The first bytes' bits most likely have the following meaning (bit numbers count from LSB):

bitfunction(s)value if setvalue if unset
0 MAS poweron reset polarity low active high active
0 MAS PR polarity (only important for recording, though also present in SP firmware) high active low active
0 MAS SIBC clock invert invert don't invert
1 LCD contrast bias    
2 Necessary SCK1 level for USB mode high low
2 Clock gate logic: PA12 levels high for internal, low for external low for internal, high for external
2 Detection of bridge activity in USB mode (only) Activity: AN5 > 250 Activity: AN5 <= 400
3 (FMR only) Tuner type Philips tuner Samsung tuner

Power measurements

For adjusting the power thread's runtime estimation, I did some measurements. Conditions for all these were:

  • Ondio SP (Jens) or Ondio FM (Jörg)
  • Rockbox loaded in RAM, and RomBox (SP only).
  • Scroll speed in rockbox set to 25 Hz (speed = 14), 2 pixels per step, font = rockfont-8
  • WPS containing peak meter in high performance mode
  • VBR mp3 ~ 200 kbps on internal flash
  • Voltage: 4.6 V (resembling full batteries) and 3.0 V (resembling almost empty batteries)
Situation Current at 4.6 V Current at 3.0 V Remark
  Ondio SP Ondio FM Ondio SP Ondio FM  
  RAM ROM RAM RAM ROM RAM  
File browser, no scrolling 54 mA 54 mA 52 mA 84 mA 84 mA 79 mA  
File browser, 1 scrolling line 56 mA 58 mA 53 mA 88 mA 92 mA 81 mA  
WPS, pause, no scrolling 59 mA 60 mA 53 mA 93 mA 96 mA 81 mA  
WPS, play, no scrolling 65 mA 65 mA 57 mA 99 mA 101 mA 86 mA  
WPS, play, 1 scrolling line 65 mA 67 mA   102 mA 104 mA    
WPS, playing & loading/swapping 93 mA 85 mA 84 mA 151 mA 135 mA 134 mA RAM-based needs ~8 sec, RomBox needs ~10 sec
Video plugin, playing 65 mA 65 mA 64 mA 102 mA 102 mA 96 mA  
Video plugin, loading & playing 88 mA 84 mA 83 mA 142 mA 136 mA 129 mA RAM-based needs ~13 sec, RomBox needs ~17 sec
Jpeg viewer, displaying 63 mA 62 mA 58 mA 98 mA 98 mA 88 mA  
Jpeg viewer, decoding 87 mA 85 mA 76 mA 140 mA 137 mA 119 mA  
FM radio     66 mA     103 mA  
Recording, internal mic     82 mA     128 mA  
Archos firmware always runs from RAM
"Start menu" 90 mA   83 mA 146 mA   141 mA  
File browser 90 mA   83 mA 146 mA   142 mA  
Playback 93 mA   84 mA 151 mA   149 mA  
Loading from flash 130 mA   86 mA >200 mA   >200 mA  
FM radio     90 mA     143 mA  
Recording, internal mic     106 mA     170 mA  

Archos Firmware Issues

Archos Firmwares older than 1.31f have a bug that will brick your ondio if you format it.
Be sure to quickly update to a newer Archos Firmware, of even better, flash it with Rockbox.
See the archos changelog for more info.

another "possibility" to brick your Ondio: If you run this update from

http://www.archos.com/support/download/firmware/ondio_sp/1.32b/ajbrec.ajz

on a flashed Ondio (with bootbox) you kill your box! This file is not a normal firmware update, if you run it it shows some strings "RAZ" and" PRG" and so on and writes directly in the flash without warning! After shutdown you only see the "removable disks" in your PC, but you cannot access it.

It's possible to rescue such a box using the UART boot mod -- JensArnold

r63 - 30 Jan 2008 - 12:46:46 - MarcGuay

Revision r61 - 30 May 2006 - 09:28 - JensArnold
Revision r60 - 30 May 2006 - 08:55 - JoergBierstedt
Copyright by the contributing authors.