| 0x70002800 | |
| 0x1 (bit 0) set or cleared along with bit 28 |
| 0x2 (bit 1) set or cleared along with bit 29 |
| 0x70 (bits 4, 5, 6) enabled for input & output |
| 0x300 (bits 8, 9) |
| 0xC00 (bits 10, 11 = 01, 10, 11) |
| 0x2000000 (bit 25) |
| 0x10000000 (bit 28) enable I2S? input |
| 0x20000000 (bit 29) enable I2S? output |
| 0x80000000 (bit 31) soft reset (clear to finish) |
| 0x70002804 | |
| 0x40000000 I2S? busy? |
| 0x7000280c | I2S? fifo |
| 0x1 (bit 0) set for output |
| 0x2 (bit 1) cleared for output |
| 0x10 (bit 4) set for input |
| 0x20 (bit 5) cleared for input |
| 0x100 (bit 8) set for output |
| 0x1000 (bit 12) set for input |
| 0x3F0000 fifo out empty count |
| 0x3F000000 fifo in empty count |
| 0x70002840 | I2S? fifo out |
| 0x70002880 | I2S? fifo in |