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Wiki > Main > STMP37xxPins (compare)

Difference: STMP37xxPins (r2 vs. r1)

STMP37xx Pins


Overview

This page summarizes the different pin functions of the STMP37xx. There are two variants: the STMP3700 and the STMP3780 (aka IMX233). The STMP3700 is a generic name for the STMP3700, STMP3710, STMP3760, STMP3770 and some other variants. Each variant has a 169BGA and a LQFP128 version but we only refer to the BGA169 one because this the only one we have seen. The table below summarizes the different packages of the different chips known.

ChipSTMP3710STMP3731STMP3738STMP3750STMP3760STMP3770STMP3780
LQFP Package 100-pin128-pin128-pin128-pin128-pin100-pin128-pin
BGA Package 100-pin169-pin169-pin169-pin169-pin100-pin169-pin

Important Note: it is unclear whether the 100-pin packages use a different pin map or not since. The CreativeZENStyleM300 uses a 100-pin LQFP package.

Generation

These tables were computer generated using the attached program. If you find any error, please report it to AmauryPouly or on the irc channel.

STMP3780/IMX233 BGA169

This table is based on the i.MX233 documentation.

Bank 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mux Reg 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
select = 0 gpmi_d15gpmi_d14gpmi_d13gpmi_d12gpmi_d11gpmi_d10gpmi_d9gpmi_d8gpmi_d7gpmi_d6gpmi_d5gpmi_d4gpmi_d3gpmi_d2gpmi_d1gpmi_d0
select = 1 auart2_txauart2_rxlcd_d23lcd_d22lcd_d21lcd_d20lcd_d19lcd_d18lcd_d15lcd_d14lcd_d13lcd_d12lcd_d11lcd_d10lcd_d9lcd_d8
select = 2 gpmi_ce3n       ssp1_d7ssp1_d6ssp1_d5ssp1_d4ssp2_d7ssp2_d6ssp2_d5ssp2_d4ssp2_d3ssp2_d2ssp2_d1ssp2_d0
select = 3 gpiogpiogpiogpiogpiogpiogpiogpiogpiogpiogpiogpiogpiogpiogpiogpio
 
Bank 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mux Reg 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
select = 0 i2c_sdi2c_clkauart1_txauart1_rxauart1_rtsauart1_ctsgpmi_rdngpmi_wrngpmi_wpngpmi_rb3gpmi_rb2gpmi_rb1gpmi_rb0gpmi_ce2ngpmi_alegpmi_cle
select = 1 gpmi_ce2ngpmi_rb2ir_out_datair_in_datair_clk                 gpmi_a2lcd_d17lcd_d16
select = 2 auart1_rxauart1_txssp1_d7ssp1_d6ssp1_d5ssp1_d4   ssp2_sck       ssp2_cmdssp2_det      
select = 3 gpiogpiogpiogpiogpiogpiogpiogpiogpiogpiogpiogpiogpiogpiogpiogpio
 
Bank 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mux Reg 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
select = 0 lcd_d15lcd_d14lcd_d13lcd_d12lcd_d11lcd_d10lcd_d9lcd_d8lcd_d7lcd_d6lcd_d5lcd_d4lcd_d3lcd_d2lcd_d1lcd_d0
select = 1 etm_da7etm_da6etm_da5etm_da4etm_da3etm_da2etm_da1etm_da0etm_da15etm_da14etm_da13etm_da12etm_da11etm_da10etm_da9etm_da8
select = 2 saif1_d1saif1_d2saif2_d2saif2_d1saif_lrclksaif_bitclksaif1_d0saif2_d0                
select = 3 gpiogpiogpiogpiogpiogpiogpiogpiogpiogpiogpiogpiogpiogpiogpiogpio
 
Bank 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mux Reg 3 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
select = 0   pwm_4pwm_3pwm_2pwm_1pwm_0lcd_vsynclcd_hsynclcd_enablelcd_dotclklcd_cslcd_wrlcd_rslcd_resetlcd_d17lcd_d16
select = 1   etm_tclketm_tctlgpmi_rb3timrot2timrot1lcd_busyi2c_sdi2c_clkgpmi_rb3     etm_tclketm_tctl    
select = 2   auart1_rtsauart1_cts   duart_txduart_rx               gpmi_ce3n   saif1_alt_bitclk
select = 3   gpiogpiogpiogpiogpiogpiogpiogpiogpiogpiogpiogpiogpiogpiogpio
 
Bank 2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mux Reg 4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
select = 0 emi_a06emi_a05emi_a04emi_a03emi_a02emi_a01emi_a00timrot2timrot1ssp1_sckssp1_d3ssp1_d2ssp1_d1ssp1_d0ssp1_detssp1_cmd
select = 1               auart2_ctsauart2_rts     i2c_sdi2c_clk   gpmi_ce3n  
select = 2               gpmi_ce3nspdifjtag_trst_njtag_tmsjtag_rtckjtag_tckjtag_tdiusb_otg_idjtag_tdo
select = 3 gpiogpiogpiogpiogpiogpiogpiogpiogpiogpiogpiogpiogpiogpiogpiogpio
 
Bank 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mux Reg 5 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
select = 0 emi_wenemi_rasnemi_ckegpmi_ce0ngpmi_ce1nemi_ce1nemi_ce0nemi_casnemi_ba1emi_ba0emi_a12emi_a11emi_a10emi_a09emi_a08emi_a07
select = 1                                
select = 2                                
select = 3 gpiogpiogpiogpiogpiogpiogpiogpiogpiogpiogpiogpiogpiogpiogpiogpio
 
Bank 3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mux Reg 6 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
select = 0 emi_d15emi_d14emi_d13emi_d12emi_d11emi_d10emi_d9emi_d8emi_d7emi_d6emi_d5emi_d4emi_d3emi_d2emi_d1emi_d0
select = 1                                
select = 2                                
select = 3 disableddisableddisableddisableddisableddisableddisableddisableddisableddisableddisableddisableddisableddisableddisableddisabled
 
Bank 3 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mux Reg 7 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
select = 0                     emi_clknemi_clkemi_dqs1emi_dqs0emi_dqm1emi_dqm0
select = 1                                
select = 2                                
select = 3                     disableddisableddisableddisableddisableddisabled
 

STMP3700 BGA169

This table is based on the linux code available plus some reverse engineering, its content might not be reliable.

Bank 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mux Reg 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
select = 0 gpmi_d15gpmi_d14gpmi_d13gpmi_d12gpmi_d11gpmi_d10gpmi_d9gpmi_d8gpmi_d7gpmi_d6gpmi_d5gpmi_d4gpmi_d3gpmi_d2gpmi_d1gpmi_d0
select = 1                                
select = 2                                
select = 3 gpiogpiogpiogpiogpiogpiogpiogpiogpiogpiogpiogpiogpiogpiogpiogpio
 
Bank 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mux Reg 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
select = 0     auart2_txauart2_rxauart2_rtsauart2_ctsgpmi_rdngpmi_wrngpmi_irqgpmi_resetngpmi_rb3gpmi_rb2gpmi_rb0gpmi_a2gpmi_a1gpmi_a0
select = 1                                
select = 2                                
select = 3 gpiogpiogpiogpiogpiogpiogpiogpiogpiogpiogpiogpiogpiogpiogpiogpio
 
Bank 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mux Reg 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
select = 0 lcd_d15lcd_d14lcd_d13lcd_d12lcd_d11lcd_d10lcd_d9lcd_d8lcd_d7lcd_d6lcd_d5lcd_d4lcd_d3lcd_d2lcd_d1lcd_d0
select = 1                                
select = 2                                
select = 3 gpiogpiogpiogpiogpiogpiogpiogpiogpiogpiogpiogpiogpiogpiogpiogpio
 
Bank 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mux Reg 3 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
select = 0       ssp1_detssp1_d3ssp1_d2ssp1_d1ssp1_d0ssp1_sckssp1_cmdlcd_busylcd_enablelcd_rslcd_wrlcd_rslcd_reset
select = 1                                
select = 2                                
select = 3   gpiogpiogpiogpiogpiogpiogpiogpiogpiogpiogpiogpiogpiogpiogpio
 
Bank 2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mux Reg 4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
select = 0 emi_ce3nemi_ce2nemi_ce1nemi_ce0nemi_casnemi_rasnemi_cketimrot2timrot1i2c_sdi2c_sclpwm_4pwm_3pwm_2pwm_1pwm_0
select = 1                                
select = 2                                
select = 3 gpiogpiogpiogpiogpiogpiogpiogpiogpiogpiogpiogpiogpiogpiogpiogpio
 
Bank 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mux Reg 5 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
select = 0 emi_wenemi_a14emi_a13gpmi_a12gpmi_a11emi_a10emi_a08emi_a08emi_a07emi_a06emi_a05emi_a04emi_a03emi_a02emi_a01emi_a00
select = 1                                
select = 2                                
select = 3 gpiogpiogpiogpiogpiogpiogpiogpiogpiogpiogpiogpiogpiogpiogpiogpio
 
Bank 3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mux Reg 6 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
select = 0 emi_d15emi_d14emi_d13emi_d12emi_d11emi_d10emi_d9emi_d8emi_d7emi_d6emi_d5emi_d4emi_d3emi_d2emi_d1emi_d0
select = 1                                
select = 2                                
select = 3 disableddisableddisableddisableddisableddisableddisableddisableddisableddisableddisableddisableddisableddisableddisableddisabled
 
Bank 3 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Mux Reg 7 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
select = 0                     emi_clknemi_clkemi_dqs1emi_dqs0emi_dqm1emi_dqm0
select = 1                                
select = 2                                
select = 3                     disableddisableddisableddisableddisableddisabled
 

-- AmauryPouly - 06 Jul 2012

r2 - 11 Jul 2012 - 17:26:12 - AmauryPouly

Revision r2 - 11 Jul 2012 - 17:26 - AmauryPouly
Revision r1 - 07 Jul 2012 - 15:12 - AmauryPouly
Copyright by the contributing authors.