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Wiki > Main > ToshibaGigabeatSPortPins (compare)

Difference: ToshibaGigabeatSPortPins (r9 vs. r8)

Toshiba Gigabeat S Port Pin Assignments

Legend

CharacterMeaning
I Input
O Output
X Not configured as GPIO for its direction

GPIO1

Port pinI/O/XDescription
0 O MC13783 USEROFF
1 I MC13783 PWRRDY
2 I MC13783 BATTDETB
3 I  
4 I  
5 X  
6 I  
7 I  
8 I  
9 I  
10 I  
11 I  
12 I  
13 I  
14 I  
15 I  
16 I  
17 X  
18 X  
19 X  
20 X  
21 O  
22 O Connection to octal FET bus switch OE (TV Encoder)
23 I  
24 O  
25 I  
26 O Si4701 Tuner RST (RESET)
27 I Si4701 Tuner GPIO2 (SEEK END)
28 I Si4701 Tuner GPIO3 (STEREO/MONO Status)
29 O  
30 O ISP 1504 CS (PHY)
31 I MC13783 PRIINT (PMIC)

GPIO2

Port pinI/O/XDescription
32 (0) I  
33 (1) I  
34 (2) I  
35 (3) I  
36 (4) X  
37 (5) X  
38 (6) X  
39 (7) X  
40 (8) X  
41 (9) X  
42 (10) X  
43 (11) X  
44 (12) O  
45 (13) O  
46 (14) X I2C2? SCLK (Si4700 SCLK)
47 (15) X I2C2? SDA (Si4700 SDIO - GPIO during busmode select)
48 (16) O ATA_EN (Bus Switch, Level Shifter) - 0=Enabled
49 (17) I  
50 (18) X  
51 (19) X  
52 (20) X  
53 (21) X  
54 (22) I  
55 (23) I  
56 (24) I  
57 (25) I  
58 (26) O  
59 (27) O  
60 (28) I  
61 (29) X  
62 (30) X  
63 (31) X  

GPIO3

Port pinI/O/XDescription
64 (0) I  
65 (1) I  
66 (2) O  
67 (3) I  
68 (4) I Hold switch (LOCK Slide SW)
69 (5) O HDD ON/OFF (ATA poweroff)
70 (6) O  
71 (7) O  
72 (8) I  
73 (9) I  
74 (10) I Seems to be 1 for final hardware, 0 for dev boards? (based on reading bootloader ram init code)
75 (11) I Seems to be 1 for final hardware, 0 for dev boards? (based on reading bootloader ram init code)
76 (12) O   LCD RESET
77 (13) O  
78 (14) O FS456 ON/OFF (454PWRON1)
79 (15) I  
80 (16) O ISP 1504 RESET (PHY)
81 (17) I  
82 (18) I  
83 (19) I  
84 (20) I Battery Switch (slide switch)
85 (21) O Analogue LDO Enable (WM8978 AVDD, SPKVDD)
86 (22) O HEADPHONE MUTE (Turn on headphone jack output)
87 (23) O  
88 (24) O  
89 (25) O  
90 (26) X  
91 (27) X  
92 (28) X  
93 (29) X  
94 (30) X  
95 (31) X  

DVFS Pins

What is noteworthy here is that the lines are reversed from a pairing of DVFS0 to DVSSW1A? and DVFS1 to DVSSW1B? as may be expected.

Processor Signal OutputPMIC Signal InputDescription
DVFS0 DVSSW1B? DVSUP0 bit 0 in PMCR0 register to functional pin mapping
DVFS1 DVSSW1A? DVSUP1 bit 1 in PMCR0 register to functional pin mapping

Dock connector

40_pin_connector.JPG

Port pin Description Name on block diagram
1 ground  
2 data � (USB2ATA?) USB 2.0 Hi-Speed
3 data + (USB2ATA?)
4 ground  
5 line-out L Lineout
6 line-out R
7 ground  
8    
9    
10    
11    
12    
13    
14    
15    
16    
17    
18    
19    
20    
21    
22    
23    
24    
25    
26    
27    
28    
29    
30    
31    
32    
33    
34    
35    
36    
37    
38    
39    
40    

Debug connector

Port pin Description
1  
2  
3  
4  
5  
6  
7  
8  
9  
10  

View topic | View difference side by side | History: r10 < r9 < r8 < r7 | More topic actions
r10 - 05 Nov 2011 - 15:59:43 - MichaelSevakis

Revision r9 - 18 May 2010 - 23:04 - MichaelSevakis
Revision r8 - 17 Apr 2010 - 11:29 - MichaelSevakis
Copyright © by the contributing authors.