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#rockbox log for 2004-03-03

00:00:01LinusN"DIOR- signal is the strobe signal asserted to read device registers or the Data port"
00:01:20LinusNand the timing diagram clearly shows that the idle state is high
00:01:48LinusNso the DIOR- signal goes low twice in a cycle, as far as i can see
00:04:24amiconnNo, the signal does not go low twice in a cycle. As you say, the idle state is high, so you have to put it low before the first read cycle after an idle period.
00:05:34amiconnOtherwise you cannot start the cycle, because the cycle is started by the low->high transition (hm - that's means strobe)
00:06:26amiconnThe cycle starts with this transition. The signal then has to stay high at least t2. After t2, the data is vaild.
00:07:35LinusNno, i believe the cycle starts earlier, since the device may very well negate IORDY before the rising edge of DIOR
00:07:43*[IDC]Dragon raises from the schematics
00:08:01[IDC]Dragonthere's funny circuitry in there.
00:08:02amiconnThen you put the signal low for at least t2i. If after that you put it high again and the device is still selected, you immediately start the next cycle!
00:08:27 Join midknight2k3 [0] (
00:08:41[IDC]DragonI wonder if the schematics are really correct here. What a job to find this out!
00:08:43midknight2k3Linus woohoo
00:08:51midknight2k3linus i've got a VU update for you
00:09:09[IDC]Dragonread and write go in loops,
00:09:12midknight2k3hi idc
00:09:16LinusNamiconn: but the cycle time (t0) is measured between the two rising edges of DIOR
00:09:21 Nick edx{off} is now known as edx (
00:09:23 Quit edx ()
00:09:59[IDC]Dragonthere is also an enable for CS and addr derived from it
00:10:02amiconnLinusN: Yes t0 is called cycle time because the actual cycle is everything contained within it.
00:10:35midknight2k3sorry to interrupt all, Linus, can I send it?
00:10:47LinusNand the address is changing on the second rising edge
00:11:17LinusNmidknight2k3: use the patch tracker, i'm busy right now
00:12:25 Quit AciD` (Read error: 104 (Connection reset by peer))
00:12:27LinusNamiconn: so the next cycle can't start with the second rising edge of DIOR, according to the diagram
00:13:01LinusNnot if the address is supposed to be valid on all rising edges
00:18:44amiconnLinusN: I read it like that: If the address is valid at the time of the second rising edge of DIOR, another cycle starts, if not, it remains oin idle state.
00:21:37LinusNi found another timing diagram, from a Quantum data sheet:
00:21:38 Quit midknight2k3 (Read error: 104 (Connection reset by peer))
00:21:41amiconnLinusN: This is supported by a simple calculation: The cycle time t0 for PIO4 as given in the table is 120 ns. PIO4 can transfer 16.6 MB/s. IDE is 16 bit -> 8.3 million transfers/sec -> cycle time is 120 ns.
00:23:20 Join midknight2k3 [0] (
00:23:43LinusNamiconn: i get it
00:26:34[IDC]Dragonamiconn: the quantum waveforms look different, more plausible: the polarity of DIOR is inverted
00:27:09[IDC]Dragongoing low to sample the address, high for the data
00:27:27amiconnLinusN: agreed, the quantum diagram looks much clearer.
00:27:50amiconnOops, meant [IDC]Dragon.
00:28:41***Saving seen data "./dancer.seen"
00:28:58amiconn[IDC]Dragon: You did test my ATA loops and they are slower? Both for aligned and for misaligned data?
00:29:06LinusNthe IORDY setup time worries me a little
00:29:09[IDC]Dragonyes, sorry.
00:29:30[IDC]Dragonamiconn: but your bitswap is 15% faster.
00:31:13[IDC]Dragonthe ATA spec shows logic levels, not voltage levels!
00:31:41[IDC]Dragonsee 3.2.8
00:31:44amiconn[IDC]Dragon: Then this must have something to do with the ATA read not being an ordinary read, but I cannot imagine why this swaps the "speed order" of the routines.
00:32:18elinenbesome good discussion finally going on in the channel :)
00:32:26LinusNelinenbe: :-)
00:32:37[IDC]DragonLinusN: signal line at the bottom postition means de-asserted, not low
00:32:39midknight2k3it's being polluted
00:32:45midknight2k3i think i need to butt in with
00:32:48midknight2k3"hey nerds"
00:32:54midknight2k3"eat me"
00:32:55LinusN[IDC]Dragon: i get it
00:32:56midknight2k3or maybe not
00:32:58[IDC]Dragonhey troll
00:33:06midknight2k3hey idc
00:33:09midknight2k3i resent that
00:33:44midknight2k3who's up for cleaner clock code WOOHOO
00:34:10midknight2k3Linus: did you discover the boot harddrive bug yet?
00:34:13[IDC]DragonLinusN: so the world is back in order, eath circling the sun, not vice versa
00:34:20LinusNok, so that explains the long delay of the /WR signal
00:34:36midknight2k3where it spins down on boot and takes a few extra seconds?
00:35:14LinusNmidknight2k3: no
00:35:24midknight2k3ever use your fm recorder? sheesh lol
00:35:27midknight2k3or is it just mine
00:35:37LinusNit sure doesn't happen on mine
00:35:44LinusNbut i haven't flashed it
00:35:47midknight2k3humm odd
00:35:53midknight2k3oh and now mine takes a hold of on to boot
00:35:56midknight2k3may be flash related?
00:36:06LinusNcould be
00:36:17midknight2k3it spins down instantly
00:36:30midknight2k3like someone called ata_sleep(0; right at boot
00:36:48[IDC]DragonLinusN: so it looks like a normal bus cycle again.
00:37:06[IDC]DragonI recommend that quantum datasheet, page 10.
00:37:16[IDC]DragonMore legible.
00:37:25LinusNyes, a normal cycle with some constraints
00:37:53midknight2k3hmm, linus is it ok if i save the clock settings to .rockbox/.clock_settings?
00:38:02[IDC]DragonWe still have this funny 3 gata delay circuit.
00:38:06[IDC]Dragon3 gate
00:38:10midknight2k3you moved it to .rockbox/rocks/.clock_settings - just wondered why
00:39:25LinusNthat circuit delays the RD/WR signal to match the delay through the data buffer
00:39:53LinusNbut it delays the falling edge more than the rising, for some reason
00:39:56[IDC]DragonFor write, the fall edge is delayed one more than the rise.
00:40:04 Join track [0] (
00:40:25midknight2k3hi track
00:40:27[IDC]Dragonthe read is delayed by 3 but tapped.
00:40:34LinusNmy concern is the IORDY timing
00:40:58trackhi linusn
00:41:00[IDC]Dragonthe IDE_A_C comes out, which is the enable for the CS/Ax buffer
00:41:03LinusNin the quantum data sheet, tA is a min time
00:41:06midknight2k3track, I'm starting on that clock update
00:41:17midknight2k3i'll be sure to add in your remove second hand feature
00:41:30[IDC]Dragonbut the buffer has to be enabled for write as well?
00:41:53[IDC]Dragonthere must be a flaw in the schematic
00:42:06trackmid I have another idea for the second hand
00:42:45trackinstead of making it move every second, how about making it continious sweep as found on some clocks
00:43:12LinusN[IDC]Dragon: i think so too
00:44:55[IDC]Dragonwhy are you concerned about IORDY?
00:46:02LinusNbecause that is connected to the WAIT signal
00:46:33[IDC]Dragonlooks like the right thing to do
00:47:32LinusNi'm trying to figure out why our optimized code fails on certain drives
00:49:05[IDC]DragonI know...
00:49:16LinusNfor instance, what happens if the ATA cycles come back to back?
00:49:55LinusNthen the t2i time is not met
00:51:12[IDC]Dragont2i = 25ns for PIO4
00:51:40LinusNyes, but do we know how long RD stays high between accesses?
00:51:52[IDC]Dragona single clock of ours is 90 ns
00:52:46amiconnLinusN: Even in my optimized code (which really should be fast :( ) the delay between 2 reads is 4 clock cycles even without WAIT, which equals 360 ns on the recorder. This should be long enough.
00:53:57amiconns/delay/ shortest delay/
00:55:07LinusNamiconn: remember that we have WARP mode enabled
00:55:29LinusNso the ATA and the IRAM accesses run in parallel
00:56:17[IDC]DragonI think he already neglected the bus time for the write
00:57:25[IDC]DragonHow about waiting for your LA measurements? I see no progress here.
00:57:40amiconnLinusN: yes, but one instruciton needs at least one clock cycle.
00:57:41 Quit track (Read error: 54 (Connection reset by peer))
00:58:53LinusNi'm also waiting for results from Pedro
00:59:16LinusNmy latest test disables WARP to see if there's any difference
00:59:50LinusNthe SH data sheets are not clear about the warp mode
01:00:15[IDC]Dragonto my understanding, it's a write buffer
01:00:39LinusNas i see it, the external access can go on for several instructions
01:00:52[IDC]Dragonso bus writes happen in parallel to the continued execution
01:00:55LinusNand the cpu only stalls when the data is needed
01:01:19LinusNbut that may be a too complicated logic
01:01:19[IDC]Dragonwrite data is not needed
01:01:40[IDC]Dragonwrite is "fire and forget"
01:02:18LinusNthe data sheets say nothing about writes, it says "accesses"
01:02:49LinusNor rather "some accesses"
01:03:26LinusNstill, your interpretation seems very plausible
01:04:25[IDC]Dragonchapter 8.8 of the SH7032 datasheet talks about write cycles
01:04:59LinusNah, now i see it
01:06:10LinusN(how did i miss that)
01:06:23[IDC]Dragonso in case of our ATA loop, the write to the DRAM is in parallel to the continued execution.
01:06:47[IDC]DragonThe read of the ATA register would be unaffected.
01:07:08[IDC]DragonThis means my pipeline optimization does not grip.
01:07:40[IDC]DragonHmm, but the manual did mention something about pipeline stalls.
01:08:05[IDC]Dragongrip=bite, have effect
01:08:11LinusNback to square 1
01:08:36LinusNanyways, we do have a problem with really slow drives
01:09:48LinusNone really lousy thing about the ATA command set is that there is no way to find out the current PIO mode
01:10:07amiconn[IDC]Dragon: Btw., what are the speed figures of my ATA loops versus yours? How did you measure?
01:10:15LinusNso i have no way of verifying that my set_features() hack works
01:10:44[IDC]Dragonamiconn; I have a plugin that loads a big piece of a file and times that
01:12:18amiconn[IDC]Dragon: could you send this plugin to me?
01:13:02[IDC]DragonI loaded 5MB, this takes 2.46s/3.81s for my code, 3.60s/4.53s for yours, aligned/misaligned.
01:13:11[IDC]DragonSure I can send it.
01:15:05amiconn[IDC]Dragon: The figures read like you did not enable my code. It is not enabled by default because of the problems. Did you comment out the "#define PREFER_C" ?
01:17:51LinusNfeedback from Pedro just came in: still problems
01:18:11LinusNkind of expected, now that i understand the warp mode better :-)
01:19:12[IDC]Dragonpipeline optimization is still a good thing, well, just because of the pipeline nature, independent from WARP
01:19:30[IDC]Dragonamiconn: better now
01:20:14amiconn[IDC] Dragon: what timings do you get now?
01:20:46[IDC]Dragon2.09/2.52 for 5 MB
01:22:31LinusNnice indeed
01:23:09[IDC]Dragon+22% for aligned, 51% for misaligned
01:23:18elinenbethat is a huge improvement %wise.
01:23:26[IDC]Dragonmisaligned is really substantial
01:23:40elinenbeamiconn: what are you up to next? :)
01:23:43LinusNamiconn and [IDC]Dragon: which HD model do you have? and what PIO timings?
01:24:02[IDC]DragonI have a Fujitsu 60GB
01:24:28elinenbeactually has anyone seen the chinese patch that was mentioned on the mailing list in the past few days?
01:24:40midknight2k3Linus: Can you BMP2RB something for me?
01:24:51LinusNpedro's disk has really sucky PIO timings
01:24:51[IDC]DragonPIO4, 240/120ns
01:24:52amiconn[IDC]Dragon: This proves that there are WAIT for memory writes. Because I do word writes for misaliged data also (except the first one an d the last few bytes) I have half the waits.
01:25:31amiconnLinusN: I have the original IBM 20 GB
01:25:42LinusNamiconn: the DRAM doesn't use the WAIT signal
01:25:44[IDC]Dragonwhat are these timings, who tells?
01:25:44midknight2k3anyone who can work bmp2rb?
01:25:45amiconnPIO4, 240/120ns
01:26:17LinusNmidknight2k3: send it
01:26:33LinusN[IDC]Dragon: the disk debug screen
01:27:01[IDC]Dragonno, I mean where does the info come from?
01:27:19amiconnLinusN: (WAIT) - yup, I was wrong.
01:28:03LinusN[IDC]Dragon: from the IDENTIFY DEVICE command
01:29:27[IDC]Dragonamiconn: about your code: you can always assume multiples of 512 bytes, no less
01:30:09midknight2k3sent linus
01:31:36amiconn[IDC]Dragon: ok, then I could save some instructions, code will be shorter
01:32:07amiconn[IDC]Dragon]: but not measurably faster
01:32:13[IDC]Dragonit became pretty large, IRAM is precious
01:33:03[IDC]Dragonbtw, LinusN, do you see a way to get parts of the C runtime into IRAM?
01:33:18LinusNto save IRAM, we can move out the descramble code
01:33:35[IDC]Dragonespecially the "shift by n bits" subroutine
01:33:36LinusNwhich part of it?
01:34:52LinusNthat is part of the gcc
01:35:08[IDC]DragonI know
01:35:19LinusNit would probably take a gcc patch to pull that off
01:35:57[IDC]Dragonthe whole CRT is quite small, is it possble to specify its location?
01:36:15[IDC]Dragon(just wondering)
01:37:50[IDC]DragonI can also take some other code out of IRAM
01:38:10midknight2k3i mean
01:38:11midknight2k3carry on
01:38:28[IDC]Dragonthe old lcd_write() is still in, but does only control values by now
01:38:31midknight2k3thanks linus!
01:39:13[IDC]Dragonit also has the unrolled bit loop, which is also not really needed any more.
01:39:18midknight2k3wow really
01:39:21midknight2k3must be a bug
01:39:26midknight2k3i ALWAYS get bit depth errors
01:39:28midknight2k3i knew it
01:39:30midknight2k3i just knew it
01:39:49midknight2k3hmm i'll have a look at it
01:40:59LinusN[IDC]Dragon: you should be able to load _ashiftrt.o in a different section
01:41:13midknight2k3uh oh
01:42:31[IDC]DragonOne day I'll to a re-org of the IRAM ;)
01:44:00LinusNregarding the PIO timing issue, it seems like I am on to something
01:44:14 Quit mecraw__ ("Trillian (")
01:44:21LinusNif Pedro's reports are accurate
01:45:34[IDC]Dragoncan you refine "something"? ;)
01:48:04 Quit scott666 ("i'll be back...eventually...")
01:48:56LinusNwell, it *looks* like my PIO4 mode hack works, but only until the drive spins down
01:50:06LinusNi may very well be wrong, though
01:50:22LinusNi wish i had his hard drive...
01:51:46LinusNhis HD has a min access time of 400ns when IORDY is disabled
01:52:45midknight2k3400 nanoseconds?!
01:53:13LinusNthe maximum cycle time we can achieve is 5 clocks
01:54:13[IDC]Dragonsouns sufficient
01:54:42[IDC]Dragonamiconn: got the plugin?
01:54:58midknight2k3linus, one more bmp2rb go? :D
01:56:06amiconn[IDC]Dragon: yes, thank you
01:56:36[IDC]Dragonit was originally meant for something else, testing the mp3 playback from a plugin
01:56:59[IDC]DragonI only abused it because it loads a big chunk
01:57:43midknight2k3Linus, sent. Thanks if you can
02:01:04*[IDC]Dragon needed to go to sleep like 2 hours ago
02:01:10midknight2k3nite idc!
02:01:18midknight2k3have fun with ATA crap whizzing around in your head
02:01:39LinusN[IDC]Dragon: me too!
02:01:42amiconn[IDC]Dragon: I just took out some check instructions from my ata loop. saves 20 bytes.
02:01:55midknight2k3"hmm if i give it 6 clocks i can enable the PIO4 mask and that will enable us to achieve 6MB/sec"
02:02:00midknight2k3linus THANKLS
02:02:04midknight2k3thanks* in caps
02:02:23midknight2k3yay its cool
02:02:25midknight2k3its clever logo
02:02:30midknight2k3its like a clock in the O
02:02:56midknight2k3ah last line
02:03:03midknight2k3looked like a sad winking face
02:03:32[IDC]Dragongoodnight, I mean
02:03:38midknight2k3ata woohoo
02:03:39midknight2k3go idc
02:03:40midknight2k3and video
02:03:41DBUGEnqueued KICK midknight2k3
02:03:41midknight2k3and blit
02:03:42midknight2k3and yay
02:03:44midknight2k3and flash
02:03:45midknight2k3and woohoo
02:03:49 Quit [IDC]Dragon ()
02:03:52midknight2k3ah calming down now
02:05:11midknight2k3wow out of like the past 15 lines its been all me talking except for 2 others and a quit msg
02:05:17midknight2k32 other messages*
02:06:16midknight2k3Linus: i purposefully made it 112x37 so i can nick the striping code woohoo
02:06:29LinusNi'd better go to sleep too...
02:06:35midknight2k3nite linus
02:06:36midknight2k3thanks again
02:06:40midknight2k3i should fix that bug
02:06:48midknight2k3sleep good
02:06:50LinusNamiconn: nice talking to you
02:07:29amiconnLinusN: it was me a pleasure.
02:07:34amiconnNite all.
02:07:39 Quit amiconn ("Leaving")
02:07:40midknight2k3nite linus,amiconn
02:07:46 Part LinusN
02:07:49midknight2k3at least i can say nite linus
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05:53:44sarah_hI am new to this whole thing, can someone help me out with an Archos 5000
05:56:41dwihnoWhat is the issue?
05:57:30sarah_hThis past week it just stopped functioning, when you actually press play to listen to a song, it hangs and won't turn off
05:57:46sarah_hI want to change the firmware on it, because your site seems like a solution to my problem
05:57:56sarah_hbut i really don't understand how to go about doing this
05:58:32dwihnoThe installation is quite easy. You just place the firmware file in the root folder.
05:59:03sarah_hwhat about the old files? or the mp3's currently on there. do i need to do anything special with those?
05:59:11dwihnono, not at all
05:59:47sarah_hthanks. I am going to try doing this...hopefully it will function correctly again when I am done.
06:00:06dwihnoJust unzip the archive to the root.
06:00:13midknight2k3nice ui!
06:00:21dwihnoWhich part?
06:00:27dwihnoThe audio settings or the icon stuff?
06:00:31sarah_hok thanks
06:00:47midknight2k3 o
06:00:50 Quit sarah_h ("ChatZilla 0.9.52B [Mozilla rv:1.6/20040113]")
06:00:56midknight2k3o o
06:00:58dwihnoI've thought about cleaning it up and submitting it for review, but I haven't had the time.
06:01:07midknight2k3is it updated at all?
06:01:15midknight2k3you sent me a version about 2 months ago
06:01:21midknight2k3no, i think it was a bit longer
06:01:34dwihnoSounds reasonable. I probably did it around christmas.
06:01:50midknight2k3so it's unchanged?
06:02:26midknight2k3noticed a few bugs
06:02:33dwihnoYou don't say? :)
06:02:46midknight2k3i thought it was still WIP ;D
06:03:02midknight2k3lemme boot it sec
06:03:28midknight2k3ahh yay
06:03:29midknight2k3its the icons
06:03:56midknight2k3auto volume
06:03:59midknight2k3its busted
06:04:03midknight2k3the meter doesnt show right
06:04:11midknight2k3same for channels
06:04:17midknight2k3not really meter type stuff
06:04:27dwihnoIt's not really WIP - more a proof of concept :)
06:04:35midknight2k3and the bassboost scale is off (that is, up 10% fills it up all the way)
06:04:52midknight2k3and your menus are out of date
06:04:56midknight2k3thanks a lot zagor :D
06:05:06 Quit scott666 ("i'll be back...eventually...")
06:05:21dwihnoThe worst thing that happened was the move of the sound menu
06:05:31dwihnoNow the bookmark stuff is topmost (booo!)
06:05:38midknight2k3suxors? :)
06:06:04dwihnoYeah, if I wasn't that goddamn lazy, I would compile my own binaries with my adjustments ;)
06:06:25midknight2k3i hate doing that
06:06:33midknight2k3merge it or drop it = my motto :)
06:08:19dwihnoI don't know why the bookmark menu item was put FIRST in the list.
06:08:38dwihnoI guess the guy who did the re-arrangements was a frequent bookmark user :)
06:08:48midknight2k3yeah sucks
06:08:55midknight2k3when you do your ui
06:08:57midknight2k3it will rock
06:08:58midknight2k3so thats that
06:09:01midknight2k3period. :)
06:09:07midknight2k3how large are the icons?
06:09:11midknight2k3i can make you some
06:09:15midknight2k3or pretend ot
06:09:48dwihnoI think they are 16x16
06:09:51dwihnoOr even smaller
06:09:53dwihnoI don't know.
06:09:55dwihnoLet me check
06:09:58midknight2k3wow really
06:09:59midknight2k3they look large
06:11:11dwihnoIt was just a test
06:11:19dwihnoThey should be smaller, imho.
06:11:24dwihno10x10 perhaps
06:11:29midknight2k3they're nice
06:11:31midknight2k3i can make you some
06:11:41midknight2k3icons are my bag
06:11:42midknight2k3i mean yeah
06:12:14dwihnoIf you started making icons I would feel obliged to continue my work :)
06:13:47dwihnoyou should not spend any time before I actually make it happen.
06:14:02midknight2k3i like making icons
06:14:16midknight2k3ill make you a 10x10 pack and ... er.. give them to you next time i see you in a few months maybe
06:14:24midknight2k3just for fun
06:15:22dwihnodo so
06:15:37midknight2k3i was ordered to make icons by dwinho
06:15:40CtcpIgnored 8 channel CTCP requests in 3 hours and 13 minutes at the last flood
06:15:40*midknight2k3 passes out
06:18:31*dwihno brings the medics
06:18:57midknight2k3dwinho got *me* medics
06:19:02midknight2k3*passes out dead this time*
06:21:50dwihnoOh no! What have I done!
06:22:25midknight2k3you've talked to me directly
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06:55:08midknight2k3nite dwino
06:55:11midknight2k3dwinho* sorry
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11:30:50c0uttalate night linus ?
11:36:25LinusNit's 11:40am now
11:36:30c0uttai was watching from work :)
11:36:56c0uttaunusual to see so much european activity
11:37:07c0uttausually only the americans online
11:37:14LinusNfelt good to finally have some real tech talk in the channel, it doesn't happen that often nowadays
11:38:48LinusNwell, dwihno, Hadaka, matsl, mbr and MT are european, afaik
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11:39:56[1]c0uttai suppose you've broken most of the technical barriers now
11:40:21LinusNwell, we haven't solved the ata mystery yet
11:42:39[1]c0utta@#$% sourceforge - i've been trying to do an update for about 2 hours now
11:45:55[1]c0uttalinus, can you verify for me ?
11:46:12[1]c0uttais this an original recorder and not an fm or v2 ?
11:46:23[1]c0uttathe packaging does not look familiar
11:48:33LinusNhard to tell
11:48:53LinusNas far as i know, the V2's don't come with a blue bag
11:49:45[1]c0uttai want an original recorder, but one with usb2. my recorder is getting flakey
11:50:01[1]c0uttai have soldered the pcb's but i think they're loose again
11:50:30LinusNthen resolder again
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11:51:32LinusNthey all have the same problem, so a new one isn't going to help you, especially not if he is selling it for 2 euro :-)
11:51:51c0uttai'm not very good with an iron.
11:52:25c0uttai just want a spare recorder because i think they're the best (or have the least problems)
11:54:54c0uttado you recommend this mod:
11:55:22c0uttathe joining of the terminals
12:02:33LinusNhmmm, i'm not sure if that helps or not
12:02:59LinusNthat mod was done at the archos factory, btw
12:03:55c0uttaoh, i thought zagor did it himself
12:04:34c0uttaok, i have updated to cvs and created my patch
12:04:52c0uttai have also allowed repeats on keys in quickscreens
12:05:18dwihnoc0utta: what have you been up to?
12:05:56c0uttadwihno, integrating my NEWKEYS functionality gradually to the main source
12:06:05dwihnoc0utta: "newkeys"?
12:06:14c0uttaF2/F3 menus
12:06:25c0uttaonly F2 at the moment tho
12:06:27dwihnoconfigurable screens?
12:06:36c0uttaconfigurable menu items
12:07:02c0uttaand settings too
12:07:50c0uttado you want your volume to be set to a particular value ? when i swap from headphones to car i do this quite a lot
12:08:03c0utta50% for headphones, 88% for car
12:08:15c0uttathese are both options in my own menu
12:12:23dwihnoEvilness \o/ :)
12:12:42c0uttalinus, patch submitted
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15:29:00Acochello everyone
15:29:21AcocI am looking for an upgrade to my hd in the 6000
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15:30:12AcocI'm pretty new to laptop hds so I saw there were lots of different interfaces
15:31:20Acocwhich interface (ATA(1-6),2.5",3.5") is used in the archos
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15:32:45Quelsarukit's a 2.5" hdd...
15:33:08Ka__hey all!
15:33:23Quelsarukhi ka__
15:33:25Ka__anyone know the maker of the drives in the archos recorder 2.0?
15:33:26Acocok thanks, and does it matter about all these ATA numbers
15:33:57AcocI know in the 6000 its Toshiba
15:33:59QuelsarukAFAIK, no
15:34:19Quelsarukka__ there are several, toshiba, fujitsu, hitachi...
15:35:02Ka__i have a archos on it's way to me and i want to pick up a larger drive for it before it gets here
15:35:30AcocI'm here for the same reason but for the 6000
15:35:53Acochopefully soon to be a 40000
15:36:21Quelsarukka__ you should look specs to see which one is more silent and so on.. there are some threads on the mail list about hard disk drives.. you should also read them :)
15:37:23Ka__i have access to an ibm 80 gig and wanted to make sure it was compatible.. i'm trying to locate a list if there is one.
15:37:57Quelsaruki think that drive works
15:38:55Ka__well i'm going give it a shot anyway.. won't hurt anything..
15:39:53Quelsarukremember.. that wil void the guaranty... try the box for at least 1 month or so before modding it, just in case it's not working ok.
15:40:16Acocthats a good idea
15:40:32Ka__well i'm getting this from ebay.. and i plan on voidign the warranty the day i get it anyway :)
15:40:55AcocI know some of the solders inside were a little weak in mine
15:41:05Acocso I had to go in and fix them
15:41:31Acocthe whole side with the usb port fell off lol
15:41:32Quelsarukas you wish ka__ :)
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15:41:56Ka__well i have a few mods already planned for mine.. including flashing rockbox on it :)
15:41:58Acocbut that was right after the warranty so just be careful
15:42:25Alexpeople, my jukebox 20 GB reads *Panic* Disk:NULL...I think it's power problems again!
15:42:38QuelsarukLinus|away, i call you.. hear my cry :P
15:43:03QuelsarukAlex, batts are charged?
15:44:17Alexfully chargex+d
15:44:53Alexand it doesnt get recognized by my computer...I think the power connections are poorely soldiered
15:47:07AcocI was just saying that mine were and I had to resolder them
15:47:15Alexok, was it hard?
15:47:41Acocwell for me it was obvious there was a problem
15:47:53Acocwhen I took it apart the side fell off
15:48:09Acocwasn't even attached anymore
15:48:33Quelsaruksorry alex, i'm not a guru in these kind of issues. try asking afterwards to other, like LinusN
15:48:45Acocas for how easy it was- the jukebox was my first soldering project
15:48:46Alexthanx guys
15:49:12Acocfour easy spots not next to circuitry
15:49:20Acocmake that 6
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15:50:33Acoccya later thanks for your help
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16:14:34Alexis Linus still away?
16:15:11webmindapearently ?
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16:23:44*dwihno gasps
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20:19:23photophreakis anyone in here?
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20:39:51LinusN|awayamiconn: hi
20:39:56 Nick LinusN|away is now known as LinusN (
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20:56:54amiconnHi LinusN
20:57:00LinusNyo man
20:58:02LinusNi'm suspecting that the IORDY->WAIT signal doesn't meet the timing requirements of the SH1
20:59:18LinusNthe WAIT is sampled on the rising edge of the second cycle in the access, shortly after CS is asserted
20:59:57LinusNso the ATA device doesn't have a lot of time to reply, especially since the CS and RD/WR signals are delayed
21:00:16LinusNand the SH1 expects a setup time of 40ns
21:01:03LinusNand a hold time of10ns
21:01:18LinusN(my space key is giving up on me)
21:01:41amiconnBut why does this only influence the assembler code?
21:02:18amiconnI could imagine that it occurs because with the C code we are reading slow
21:02:55amiconn, but with the assembler code it is too fast, so the drive wants to use WAIT.
21:03:28amiconnBut you did test the assembler code with additional waits (NOPs), didn't you?
21:04:27amiconnUnfortunately, for the boxes that suffer from the ata problem, the "magic" limit is apparently 400 ns
21:04:29LinusNi don't even see the problem with my drive
21:04:52LinusNthe scary part is that this 400ns hd was factory installed
21:05:34amiconn(Minimum PIO timing without using IORDY), but we can do either 360 ns, which is too fast, the next possible timing is 540 ns
21:05:52LinusNhow much time is it between the accesses in your loop?
21:07:11amiconnbecause of instruction alignment.
21:08:21amiconnMy loops are a bit "unbalanced". Both loops copy 3 words at a time.
21:08:37LinusNwe have 90ns per cpu clock, the longest waitstate we can program is 5 clocks = 450ns
21:09:42amiconnThe word-aligned loop reads are spaced 360 ns - 360 ns - 540 ns.
21:09:44LinusNbut almost the entire first clock is wasted
21:10:46amiconnThe misaligned loop reads are spaced 540 ns - 540 ns - 720 ns.
21:11:18LinusNin the current code, we have set it to only 2 clocks
21:11:34LinusNsowe should be "safe" anyway
21:11:48LinusN(regarding your timing analysis)
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21:12:55LinusNi wonder if this is causing the dreaded file corruption when recording that some people report
21:12:55amiconn(My timing figures calculated from instruction clock cycles without wait states)
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21:13:54LinusNregardless of our timing analysis, we still need to tweak the ata driver a little bit
21:14:15LinusNit must use the slower bus timing until it has enabled PIO4
21:14:29LinusNbecause we don't know which mode the drive is in
21:16:10amiconnWe should be on the safe side if we space the reads >= 600 ns (PIO 0 timing) until advanced modes are enabled.
21:17:23LinusNi think not
21:17:27amiconnAs we cannot do exactly 600 ns, the next possibility is 720 ns (recorder) / 666 ns (player)
21:17:52amiconnWhy do you think so?
21:18:31LinusNbecause the ATA address will be invalid when the SH1 ends the access, and the data bus will change
21:19:01LinusNand the sh1 ends the access earlier than 600ns, the best we can do is 450ns
21:20:12LinusNwell, chance is that the ATA bus keeps the data "floating" when the buffer is disabled...
21:20:29amiconnBut if this causes trouble with some drive, why does the C code work then? The bus read cycle should be identical, shouldn't it?
21:20:42LinusNthat's what puzzles me
21:20:54LinusNmy theory is this:
21:21:20LinusNthe hd boots up in a fast PIO mode, with fast cycles
21:22:01LinusNbut occasionally, when the code reads the FIFO very fast, it needs to halt using the IORDY pin, prolonging the cycle
21:22:20LinusNbut the WAIT signal comes too late, and the CPU ignores it
21:22:36LinusNand performs a 120ns cycle anyway
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21:23:05LinusNand reads garbage from the data bus
21:23:11LinusNthat's my theory
21:24:06LinusNmy Hitachi drive timing is 120ns/120ns :-)
21:25:09amiconnThe strange thing is: we do not even remotely reach 120 ns. The best we can do is 360 ns within the unrolled loop.
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21:25:29amiconnmy IBM drive timing is 240ns/120ns
21:25:53LinusNno, no, forget about the inter-access timing, i'm talking about the bus cycle to the HD
21:26:25LinusNthe SH1 cpu performs the ATA bus cycle in 120ns today, if WAIT isn't asserted
21:26:27amiconnand it does not suffer from the ata problems either. I even flashed rockbox with my loop compiled in.
21:27:08LinusNso the CS0 and CS1 are deasserted after 120ns
21:27:41LinusNor rather, the DIOR/DIOW signals
21:28:30amiconnBut the bus cycle is identical between C and assembler since the very same instruction is used.
21:29:12amiconnIf I understand you correctly, you cannot slow this down without modifying the hardware.
21:29:18LinusNyes, but my theory is that the hard drive needs some time between the accesses to keep up, else it will need to use IORDY
21:29:39LinusNand IORDY doesn't work, if my theory is correct
21:31:00LinusNand i'm afraid that even the longest programmable waitstate is too short for the 400ns drive, since the first and the last clock is "wasted"
21:31:29LinusNbut the logic analyzer will probably shed some light on the matter
21:31:45amiconnIf you theory is correct we should be safe if we don't go below the minimum cycle time without flow control
21:31:47LinusNstill, i don't have a hard drive that is slow enough
21:32:19LinusNyes, but in the 400ns case, we simply can't do it
21:32:35LinusNwe need to pace the accesses as well
21:32:59LinusNso we don't force it to use IORDY
21:33:12LinusN(i.e extend the cycle to 400ns)
21:33:50LinusNtalk about wild quessing...
21:34:17amiconnAgain then - why does the C loop work? I really cannot imagine this if your theory is correct
21:34:59amiconnBtw: did you ask one of the people with "problematic" boxes which hard drive model they have?
21:35:01LinusNbecause the time between the accesses is long enough to let the drive settle between the accesses, preparing the next word to be read
21:35:22LinusNso it won't extend the cycle
21:35:39LinusNand the access is safely performed in 120ns
21:35:52LinusNno,i didn't ask
21:36:49amiconnKnowing the hard drive model should help to find such a slow thing for testing.
21:38:54LinusNwe should still be able to select which loop to use by reading the timing information
21:38:59amiconnPerhaps one of us should post a request for that info on the ml
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21:42:09amiconnWelcome back :-)
21:42:19LinusNshaky DSL
21:43:04LinusNi just posted a request on the ml
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21:50:49amiconnLinusN: As I'm atm fiddling with assembler anyway, I could prepare a less aggressively optimized version
21:51:32amiconnof the ata loop. This would be 720 ns for aligned, 810 ns for misaligned (calculated figures).
21:51:58LinusNhow much is the C loop btw?
21:52:11amiconnWith these you could prepare test builds to compare with my aggressive version.
21:53:11amiconnThe C loops are 990ns/1170ns if I calculated correctly
21:53:43LinusNok, go ahead
21:54:38amiconnBtw: there is a new "aggressive version" in the works which will be faster (only a few % this time), but not longer or even shorter (have to see)
21:55:23amiconnThe new version will assume the word count to be a multiple of 4, so less conditionals in there.
21:55:55LinusNit will always be 256 words
21:56:47amiconnOr a multiple of it as we use READ_MULTIPLE?
21:57:48LinusNof course, silly me
22:01:27amiconnStarting to code..
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23:14:23midknight2k3hi ppl
23:15:51Ka_hey midknight2k3, i finally won a bit :)
23:16:02midknight2k3hes a rockboxer
23:16:08Ka_$180 for new in box recorder 2.0
23:16:20Ka_should be in the
23:16:28Ka_errr.. should be here in the next few days..
23:16:38Ka_then i can start ripping it apart :)
23:17:24Ka_midknight2k3: so where is the screen shot i was supposed to look at last night? :)
23:17:42midknight2k3i have it
23:17:44midknight2k3its at
23:17:52midknight2k3i believe
23:18:02midknight2k3i pasted it on a billboard so it'd look very nice
23:18:26midknight2k3now it says under it "Welcome to CLOCK.ROCK 2.0b" "Loading Settings..."
23:18:45Ka_nice.. that's funny.. all of that for an 8 bit lcd displayed green scaled clock :)
23:18:56midknight2k3its 1bit
23:19:03midknight2k3GREENSCALED HAAAAAHA
23:19:05Ka_errr.. yeah 1 bit
23:19:12midknight2k3but it does 8bit
23:19:14midknight2k3movie player
23:19:23Ka_gettign used to my new happy hacking keyboard.,.
23:19:28Ka_came in today!! :)
23:19:39midknight2k3happy hacking keyboard? lol!
23:19:50Ka_i haven't used a keyboard with this layout in so many years!
23:19:59midknight2k3i wanna see
23:20:16midknight2k3is it like quick buttons on the top like "int" and "float" and "void" and "bool" etc?
23:20:22midknight2k3press it and it inserts the text?
23:20:32midknight2k3and press a button like BeginComment and EndComment
23:20:46Ka_not exactly
23:21:12Ka_it's modeled after the old unix keyboards..
23:21:27midknight2k3thats GAY
23:21:38midknight2k3and on the lower right its like "happy hacking!"
23:21:42midknight2k3its so happy it makes me sick
23:22:29Ka_well the one that i have the lite2 version doesn't have the words..
23:22:36midknight2k3is that your attempt at saving a few bucks on a keyboard? 'cos it's terrible
23:22:48Ka_i guess have to be a unix/linux boy to understand
23:22:59midknight2k3yeah "happy hacking"
23:23:04midknight2k3thats unix all right
23:23:06midknight2k3i cant decode that
23:23:06Ka_the lite2 is $60
23:23:08midknight2k3i have no hopes
23:23:13midknight2k3what the hell
23:23:19midknight2k3its a keyboard minus a capslock
23:23:24Ka_the original −− the one you saw is $130
23:23:27midknight2k3get a $10 one and drill off the capslock key
23:23:30Ka_it's a lot more than that
23:24:05Ka_yeah.. for starters the control key is moved to where it *should* be
23:24:12Ka_so is the escape key
23:24:37midknight2k3i see
23:24:39Ka_also the keys are set up the way they are so your hands aren't moving all over the place
23:24:40midknight2k3ctrl is up a key
23:24:47midknight2k3and esc is down a key
23:24:49Ka_they stay closer to the "home" [position
23:24:51midknight2k3how worth $50
23:25:30Ka_for someone who spends a LOT of time typing it's worth every cent
23:25:55midknight2k3its gay
23:26:12Ka_even if you aren't used to the layout after you get used to it you can type a lot faster and with less stress on your wrists
23:29:08Ka_sooo let me guess something here.. you're a straight windows user right?
23:29:16midknight2k3not really
23:29:20midknight2k3mandrake setup never worked on this
23:29:26midknight2k3so blah
23:29:34midknight2k3i'll have to try redhat
23:29:37midknight2k3even though i dislike it
23:29:45Ka_so what DO you use?
23:29:53midknight2k3xp right now
23:30:04midknight2k3i wish i used OS X
23:30:28Ka_so you're more of a mac user? or would like to be?
23:30:34midknight2k3no, and yes
23:30:42midknight2k3macs are nice imo
23:30:45midknight2k3just gui-nice
23:31:05Ka_ahhh well you're a GUI user.. which is what i was getting at..
23:31:17midknight2k3i like the gui of macs
23:31:27midknight2k3but i've used linux and i prefer it
23:32:06Ka_commandline or window manager?
23:32:23midknight2k3i couldn't ever permanently migrate to linux, i'd miss 3ds max 6 and bryce 5 and vegas 4
23:32:31midknight2k3windows i like
23:32:36midknight2k3cmd line would suck
23:33:38Ka_so again.. you are a gui user.. which is why you don't understand the keyboard.. i've been using computers before there were graphical GUIs
23:34:16Ka_and all you had was a command line and ascii based user interfaces.. everything was done by the keyboard and the mouse didn't next to nothing −− or just very little
23:35:15midknight2k3a "gui user"?
23:35:28midknight2k3i think 99% of people, even linux nerds, prefer a gui
23:35:39midknight2k3it doesnt have to be all mushy and slick
23:35:45midknight2k3just a gui
23:35:52midknight2k3openable/minimizable windows
23:35:54Ka_so some extent of course
23:36:01midknight2k3a small extent is all
23:36:10midknight2k3hardly a "gui user" lol
23:36:35midknight2k3ok what does rockbox need....
23:37:10Ka_i'm talking about using a keyboard for 80%+ of the operations on a computer.. instead of a mouse
23:37:58Ka_rockbox is actually a perfect example.. interfaces like that use only a pad of one form or another.. they don't need a mouse to operate
23:38:14Ka_but i'm erally talking about using the keyboard to do most of your work.
23:38:43midknight2k3thats a gui user
23:38:45Ka_when you rely on a keyboard to do most of your work and not the mouse you need a better keyboard
23:38:48midknight2k3so basically everyone
23:39:28Ka_ok.. replace GUI with mouse to make this clearer
23:39:50midknight2k3yes ma'am
23:46:49 Quit AciD` (Read error: 104 (Connection reset by peer))

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