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#rockbox log for 2015-03-30

00:02:59 Quit pamaury (Ping timeout: 248 seconds)
00:06:00 Nick kugel_ is now known as kugel (~kugel@rockbox/developer/kugel)
00:09:47 Quit [Franklin] (Ping timeout: 252 seconds)
00:10:17 Join [Franklin] [0] (~franklin@cpe-071-071-039-006.triad.res.rr.com)
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00:34:43 Join byteframe__ [0] (~byteframe@pool-71-174-15-145.bstnma.east.verizon.net)
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01:26:36***Saving seen data "./dancer.seen"
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03:26:41***Saving seen data "./dancer.seen"
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04:18:51 Quit RiD (Quit: A good plan today is better than a perfect plan tomorrow.)
04:38:27 Join Smarticles101 [0] (~Smarticle@codmadnesspro.com)
04:44:36Smarticles101Hello, when I install rockbox onto my iPod nano 2nd generation, I receive the error that there is a bad checksum
05:00
05:21:57saratogaSmarticles101: that means that the rockbox binary on the player isn't what the bootloader expects, so either its corrupted or for a different player
05:26:44***Saving seen data "./dancer.seen"
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07:26:46***Saving seen data "./dancer.seen"
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09:26:50***Saving seen data "./dancer.seen"
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10:03:43 Join pamaury [0] (~quassel@rockbox/developer/pamaury)
10:06:41wodzpamaury: The beginning of rom dump looks weird
10:07:31pamauryyes, only nops
10:08:01pamauryactual code starts at 0x1fc for some reason
10:11:12wodzpamaury: As I stated in mail you should grab rom using uncached alias 0xbfc00000
10:11:40pamauryOh, I missed your email sorry
10:12:41pamauryOk, I'll try to dump it today but I won't have much time to work on this in the next two weeks, it's the final straight line before submitting my PhD ^^
10:14:56 Join petur [0] (~petur@rockbox/developer/petur)
10:16:03wodzpamaury: backlight is likely controlled by PWM and corresponding pin is e1
10:31:33pamauryok, how does mips memory mapping works ? is there a standard pattern for cached vs uncached ?
10:36:47 Quit pamaury (Ping timeout: 252 seconds)
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10:47:39 Quit foolsh (Remote host closed the connection)
10:51:54 Join foolsh [0] (~quassel@c-67-174-139-237.hsd1.in.comcast.net)
11:00
11:01:12wodzpamaury: (logs) https://books.google.pl/books?id=sTDHUr4eGYIC&pg=PA67&lpg=PA67&dq=mips+kseg+segments&source=bl&ots=_cI26vxpSK&sig=EU3JUuDA56uNXgu_YngM-t2K400&hl=en&sa=X&ei=kBAZVYiQAoevPJ_DgCA&ved=0CDEQ6AEwAg#v=onepage&q=mips%20kseg%20segments&f=false
11:03:25 Quit foolsh (Remote host closed the connection)
11:03:58wodzpamaury: (log) BUT basically 0x80000000 - 0x9fffffff is cached low 512MB of address space NOT translated by MMU, 0xa0000000 - 0xbfffffff is uncached low 512MB of address space NOT translated by MMU. (or statically mapped one could say)
11:04:49 Quit d33tah (Ping timeout: 272 seconds)
11:05:59 Join foolsh [0] (~quassel@c-67-174-139-237.hsd1.in.comcast.net)
11:06:10 Join pamaury [0] (~quassel@rockbox/developer/pamaury)
11:06:14wodzpamaury: (log) 0x00000000 - 0x7fffffff is MMU mapped (can be cached or uncached depending on MMU setup) available to userspace, 0xc0000000 - 0xffffffff is MMU mapped available to kernel
11:07:21pamauryok thanks, I didn't understand what kseg was referring to in the manual, now it's clearer
11:07:43wodzpamaury: (log) simple embedded systems use region starting at 0x80000000 for main memory and 0xb0000000 for I/O space
11:08:00wodzotherwise you need to setup MMU
11:12:02wodzso for simple system: 0x00000000 - 0x1fffffff (phy) = 0x80000000 - 0x9fffffff (cached) = 0xa0000000 - 0xbfffffff (uncached)
11:26:52***Saving seen data "./dancer.seen"
11:28:47pamaurywodz: then isn't it a bit weird to have the dcache mapped at 0x80000000 on this device ?
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11:30:16 Join d33tah [0] (~d33tah@kolos.math.uni.lodz.pl)
11:30:23pamauryalso the usb boot procedure is a bit weird (at least in the description): one can load data at any address but the doc says for the first stage it will copy data from D-cache to I-cache. So I assume one needs to load the code at the mapped address of the dcache, but I don't get this "copy code from D-cache to I-cache" thing
11:30:42pamaurymaybe it's just the formulation
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13:16:56 Join mortalis [0] (~kvirc@212.44.150.238)
13:26:56***Saving seen data "./dancer.seen"
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13:41:03 Quit mortalis (Ping timeout: 245 seconds)
13:46:47wodzpamaury: https://github.com/gcwnow/ingenic-boot/tree/master/source
13:58:53 Quit AlexP (Remote host closed the connection)
13:59:19pamauryah by the way, I realised than the reason why the IHFS image has interesting things beginning at the fourth sector only: because the first 4 sector contain the ingenic bootloader loaded by the ROM
14:00
14:00:24pamaury*that
14:05:58wodzI think the only reasonable explanation for d/i cache mapping is that it is not physically mapped anywhere. Its just fresh (I suspect boot rom flushes it all and since rom cache runs from uncached alias it is not filled).
14:06:07 Join TheLemonMan [0] (~lemonboy@unaffiliated/thelemonman)
14:06:53wodzso when you do any data transfer to mem in cached region it will stay in cache and will not touch memory (which is not present at this stage yet)
14:07:33wodzpamaury: ^
14:08:16wodzthe question is how icache is synchonized with dcache
14:08:44wodzit must be inter-cache synchronization and not flush and refill
14:08:45pamauryyeah that's possible, anyway it would be interesting to disassemble the ROM to see how it works
14:08:58pamaurypossibly some CPU specific cache operation
14:10:11 Join AlexP [0] (~alex@rockbox/staff/AlexP)
14:10:24wodzmost probably. Cache operations are slightly different to the regular MIPS
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15:26:59***Saving seen data "./dancer.seen"
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15:31:09 Nick byteframe__ is now known as byteframe (~byteframe@pool-71-174-15-145.bstnma.east.verizon.net)
15:31:16 Quit byteframe (Quit: Deuces.)
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17:14:18 Quit einhirn (Quit: Miranda IM! Smaller, Faster, Easier. http://miranda-im.org)
17:27:02***Saving seen data "./dancer.seen"
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