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#rockbox log for 2015-10-26

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09:55:20wodzI am analyzing atj213x recovery session. On quite early stage PC program uploads file called PDCDEC.DSP. The format of this file is pretty peculiar :-)
09:56:46wodzData are organized in 0x200 bytes chunks. Each chunk consist of 3 subchunks 0xaa bytes each. One of the subchunk is coded data and 2 others are key array. The data are reconstructed as OutByte = InByte^key1^key2
09:57:31wodzSo the actual payload is only 1/3 of the transfered bytes.
09:58:07wodzI can't wrap my head why they did that like this.
10:00:44wodzAh, and DSP instructions are 24bytes so there are 3 separate blocks transfered which are then placed in memory so to form 24bit opcodes
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12:02:29wodzpamaury_: Have you ever heard about 'column mode' in dma engine?
12:02:53pamaury_no specifically no
12:03:36pamaury_I guess for a 2D dma that could mean copying data in column order rather than row order. Maybe it has to do with storage order of 2D array ?
12:03:43pamaury_where did you find that ?
12:06:01wodzdma engine is used to transfer and organize data in a way that it forms 24bit opcodes for DSP. There are 3 subsequent dma transactions where dst address is shifted one byte
12:06:36wodzI suspect that 1st block is HI byte, 2nd is MIDDLE byte 3rd is LOW byte (or other way around)
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12:07:33pamaury_maybe column mode is like having stride on the output
12:07:55pamaury_ie you copy first byte to dst, second to dst+off, third to dst+2*off and so on ?
12:08:05wodzmaybe but there is no stride len parameter anywhere
12:08:32pamaury_is it disassembly or is the code somewhere ? you have the datasheet ?
12:08:40wodzpamaury_: It looks like it first it transfers all HI bytes then all MIDDLE bytes and finally all LOW bytes
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12:09:23pamaury_yeah but how does it know the stride is 3 bytes ?
12:09:56wodzI have ds of atj213x but is very generic. There is no documentation for DSP. Copy code is from disassembly
12:14:49pamaury_wodz: can you send me the ds ? I sem to have lost it
12:15:53wodzpamaury_: only DS?
12:16:11pamaury_and code too
12:19:00wodzits gonna be bulky
12:19:21wodz~350MB :-)
12:19:29pamaury_the DS ? or the code ? You don't need to send me all the code, just that part
12:20:35wodzall materials about atj213x I have
12:21:32wodzDS is 3.5MB total
12:23:23pamaury_just DS and this part of code then :)
12:25:13wodzyou mean the code to send data to DSP?
12:26:14wodzAs I said earlier this comes from disassembly
12:26:32pamaury_can you copy the disassembly ? or just send the DS
12:27:16wodzI'll send you DS, and later today I'll send you disasm (I have it on different computer)
12:27:23pamaury_ok thanks
12:29:00wodzI can send you pcap file from reflash session as well
12:35:56wodzpamaury_: you should have it in your mailbox
12:36:06pamaury_wodz: I have it. I have another idea
12:36:26pamaury_I assume that if you send data to the DSP, you send it to DSP ram ?
12:37:09wodzIn this particular case, yes
12:37:39wodzit is copied to iram which is then mapped to DPS's instruction memory
12:39:46pamaury_I think there are two distinct things, but I am not sure. The datasheet says:
12:39:46pamaury_SRAM can be map 24k*32bit (for MIPS) or 32k*24bit (for DSP). It cn be opearted in byte.
12:39:46pamaury_It is reasonable to think that the SRAM is addressed by column:row address (just like DRAM). Row is byte access, column is 24bit in DSP mode and 32bit in MIPS mode.
12:39:46DBUGEnqueued KICK pamaury_
12:39:46pamaury_So if you send data to the SRAM in DSP mode with column mode, you increment column instead of row after each access, that gives you 3 byte stride
12:41:41wodzmakes sense
12:42:06pamaury_(admitedly, this is a bit weird because I would rather call this row mode, since usually a column is used for bytes and row for page)
12:42:45pamaury_A very simple test would be to play with DSP/MIPS mode and row/column mode with the dma see if that matches
12:43:17wodzI need to fireup hwstub and test it
12:49:27wodzbut you highlighted very important point - it is not that last byte from MIPS mapping is discarded the organization is changed when in DSP mode
12:50:13pamaury_yes I think so. Also the doc suggest you can use MIPS in source and DSP in destination or any mixture of MIPS/DSP in source or dest, even use column in source and/or destination
12:56:34wodzI think there are even more possibilities. Look at SRAMOC_CTL description - bit2 sets word size (so I think it influence stride len in fact)
13:03:30pamaury_wodz: that was what I was refering to (DSP mode versus MIPS mode). However this is confusing because the DMA has a "DSP mode" which I don't know what it does. So yeah I think SRAM_LOC controls "column size" and thus stride length in column mode. I have no idea what "DSP mode" in DMA_MODE does
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13:45:37wodzpamaury_: as far as I can tell "DSP mode" in DMA_MODE is not used at all
13:45:56wodzpamaury_: I mean I didn't hit any code which sets this
13:49:57wodzpamaury_: So simple test would be to clear iram buf, set SRAMOC_CTL to DSP mode and transfer 0x11223344, then switch to MIPS mode and read back that buffer, right?
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14:35:55pamaury_wodz: exactly.
14:36:38pamaury_the expected result would be 0x11 0x00 0x00 0x22 0x00 0x00 0x33 ... in DSP mode ad 0x11 0x00 0x00 0x00 0x22 ... in MIPS mode. all of it in column mode of course
14:43:04wodzpamaury_: exactly
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19:43:13Guest75939ref:[Saint]I'm getting filled with idea of a virtual keyboard embedded in the bootloader and entering a decryption key by hand every boot. > maybe using keypess Sequence like Konami Code
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22:09:14buckkethey guys, any chance the iPod Classic hold switch fix ( will be merged soon?
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