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#rockbox log for 2017-12-13

00:11:59 Quit pamaury (Ping timeout: 248 seconds)
00:37:29 Quit ender (Quit: You this read wrong.)
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01:18:59***Saving seen data "./dancer.seen"
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02:23:07 Quit xorly (Ping timeout: 256 seconds)
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02:32:54fs-bluebot_Build Server message: 3New build round started. Revision c8564f1, 273 builds, 12 clients.
02:42:35__builtinsomeone have a color target with more than 6 buttons that's willing to test Duke3D?
02:43:07__builtinit should handle any number of buttons gracefully now
02:50:51fs-bluebot_Build Server message: 3Build round completed after 1077 seconds.
02:50:52fs-bluebot_Build Server message: 3Revision c8564f1 result: All green
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08:17:06 Join ender` [0] (krneki@foo.eternallybored.org)
08:24:44 Join wodz [0] (~wodz@95.48.63.138)
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09:35:30wodzpamaury: (log) https://blog.avast.com/avast-open-sources-its-machine-code-decompiler
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10:18:21 Join pamaury [0] (~pamaury@rockbox/developer/pamaury)
10:31:45pamaurywodz: cool :) I'll have to try that :)
10:41:19 Quit jhMikeS (Ping timeout: 248 seconds)
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10:48:06wodzpamaury: I am playing with mmu and it a pain to do it right :/
10:48:13wodz*it is
10:58:09pamaurywodz: my mips lib: pamaury/9928cb91eafcb25ce3a2de1eb93cc17b">https://gist.github.com/pamaury/9928cb91eafcb25ce3a2de1eb93cc17b
10:58:19wodzpamaury: will look
10:58:20pamaurythere is a macro for MMU that is completely generic
10:58:44pamauryexample use:
10:58:44pamaury map_address DRAM_ORIG, PHYSICAL_DRAM_ADDR, DRAM_SIZE, K_CacheAttrCN, (16 * 1024 * 1024)
10:58:52pamaury(map dram as cacheable using 16M pages)
11:00
11:00:27 Join LinusN [0] (~linus@giant.haxx.se)
11:02:04wodzpamaury: my idea is to 1) create PTEs and store it at the bottom of DRAM. iriver e150 has 8MB dram + 96k iram so this fits in 20k considering 'recommended' mips PTE layout and 4k pages. 2) create wired entries for PTEs (3 in this case) 3) use the most simple TLB refill handler as described in 'See MIPS run
11:02:35wodzpamaury: I mean at least for testing purpose to catch what is overwriting codec buffer
11:09:03pamauryI seee, that would be cool but indeed quite a bit of work to debug this
11:09:08CtcpIgnored 1 channel CTCP requests in 0 seconds at the last flood
11:09:08*pamaury has to go
11:10:13 Join cela [0] (c24b1872@gateway/web/freenode/ip.194.75.24.114)
11:11:21cela_builtin I can test duke3d on Sony nwz-e384
11:13:32 Quit pamaury (Ping timeout: 256 seconds)
11:16:15 Quit cela (Quit: Page closed)
11:19:16***Saving seen data "./dancer.seen"
11:20:34wodzpamaury: (log) in your lib mmu_init uses mips32r2 instruction (ext)
11:21:33wodzpamaury: (log) Scratch that. on r1 appropriate macro is defined just above
11:34:59wodzpamaury: relocation can be done cleaner on mips32r2 exploiting synci instruction
11:56:48 Join pamaury [0] (~pamaury@rockbox/developer/pamaury)
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12:59:58pamaurywodz: synci is mips32r2 only
13:00
13:00:15wodzpamaury: yes, thats what I said
13:00:28pamauryah yes sorry :)
13:01:02pamauryyes I didn't finish everything for both r1 and r2 (since I don't have r2 hardware).
13:01:26pamauryAlso my relocation code seems to have a problem,if the source and destination overlap too much, the code fails to load, I didn't have to investigate it
13:03:03 Quit tchan (Quit: WeeChat 1.6)
13:03:05pamauryalternatively I guess I could provide a macro for synci based on cache hit write back and hit invalidate?
13:04:45wodzpamaury: I use this: http://paste.debian.net/1000514/
13:05:01wodzpamaury: It exploits the fact that cacheline is 16b
13:05:44pamauryyeah I saw your code, I should switch to this (or Nb at a time where N is the cache line)
13:06:09pamaury(with t0-t7 we can do 32 bytes)
13:07:11pamauryalso your code (and mine) probably both break if the source and destination overlap and destination is higher than source (the code should copy backward from the end in this case)
13:09:01wodzyeah
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