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#rockbox log for 2020-09-15

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06:53:38speachy_bilgus: Good references: https://www.kernel.org/doc/htmldocs/writing_musb_glue_layer, and linux/drivers/usb/musb/{jz4740.c,musbhsdma.c}
06:54:22speachyIngenic used a bone-stock MUSB HDRC implementation, along with the Inventra DMA implementation.
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09:22:53speachyalmost have it. it's successfully probing the mass storage device but failing to mount
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10:21:09speachyok, got it! DMA is operational on the SEND side. firing up sysbench to stress it a bit..
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10:42:57speachy_bilgus:g#2746
10:44:31speachybenchmarks apparently unaffected. Hmm.
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11:06:19speachythe RX side is going to be the same basic rework structure but with more complex rules.
11:11:03_bilgushaha thats funny that kernel.org thing is what I was reading last night talk about serendipitous
11:18:19_bilgusspeachy very nice the removal of magic numbers helps alot
11:22:38speachyit also makes it clear what's needed to better genericize the DMA −− we can have eight different endpoints with DMA at once.
11:23:38speachyat least this driver is arguably useful beyond the jz4760, should we find another SoC that uses the same DMA engine
11:23:49speachys/DMA/DMA+USB/
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11:44:46_bilgusso thats odd, the reads / writes are still within that 5% range but the seq write halved in latency and Rand r/w doubled
11:45:07speachyI'd have expected no change at all in writes.
11:45:35speachysince only device->host transfers were DMA-enabled.
11:46:04speachyI do need to re-enable the logging and see what kind of transfer sizes we're actually using.
11:47:14speachy(and if mode1 DMA transfers are being used at all..)
11:48:05_bilgusI'm guessing its bypassing your code
11:52:14_bilgus((unsigned long)ptr & 4 == 0)
11:53:02speachywhoops, that should be &3
11:54:23speachyno change in sequential read.
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12:09:25speachyhuh, I think it's using DMA only for the first transfer, and PIO for the remainder.
12:17:02speachyokay I must be having a major brain fart but that (ptr & 3 == 0) test is responsible for skipping dma from ever being used. but based on the log messags of the addresses used, that test is always true..
12:18:21speachy(the buffer always seems to be 16-byte aligned)
12:26:21_bilguswell removing it makes it now want to connect on usb plug
12:26:35speachyclearly badness remains.
12:26:38_bilgusnot*
12:34:16_bilgushmm it looks like transfer speeds drop in half after a ROLO
12:35:45_bilgusmaybe just a coincidence i'll restart and try again
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12:36:51speachyI haven't noticed that
12:44:50_bilgusnah happening after a restart too maybe somethings up with the pc
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13:08:31_bilgushmm yeah I can't get the opriginal speeds back even with the hold switch WEIRD
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13:25:20speachywith the hold switch I was seeing completely identical behavior+performance.
13:26:16_bilgusI'm going to revert to head and try again
13:27:31speachyjust pushed a new version of the patch, with some fixes but also disables DMA completely by default now.
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13:32:33_bilgusbetter than whern it started even if it does still have issues
13:33:24speachygotta put it all aside again for a while.
13:33:53_bilgusI'll play with it wed night and see what I can figure out
13:37:09_bilgusok speeds are back @ HEAD so perhaps something isn't quite right
13:37:28speachythere are zero functional changes with dma disabled
13:38:11_bilguswell you'd think the hold switch would reflect that then no?
13:38:44speachyI'd expect so, yeah. but please try with the most recent patch as the baseline (it compiles out the DMA code altogether)
13:39:02_bilgusok
13:41:01_bilgusgotta head out of town, Ill be sure to do some more testing / tweaking
13:41:32speachyI think I'll be able to poke at this again tonight. weather is crappy so it's indoor activities instead.
13:42:08speachythe linux driver is structured very differently so it's difficult to suss out some of the more subtle sequencing issues.
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15:54:20speachygot mode0 working for small transfers. big transfers (mode 1) are going into never-never land.
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16:48:45speachywell. looks like the hardware doesn't support large TX transfers. Feature flag in the core says it's not implemented.
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17:31:01speachy_bilgus: code updated. considerably restructured.
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17:42:33speachystill ahven't found why mode1 isn't working. max dma is 1MB, and the HW is suppsoed to just work. best guess is that there's some other setup bit missing.
17:42:42speachybut that's a problem for another time.
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20:13:13speachydma transferred the first block.. and the USB core seems to be ignoring it.. kicking back an underrun error for some reason
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22:02:13speachy_bilgus_: just pushed working DMA USB TX. sequential reads jumped up about 33%, from 6.6->8.8MB/s
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22:11:18speachygiven the substantial DMA overhead, it's debatable if it's worth using DMA for smaller tranfer sizes, but it's not like we're multitasking when operating as a USB device.
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