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#rockbox log for 2021-03-30

00:01:50***Saving seen data "./dancer.seen"
00:05:08_bilgus_ah got it thankfully daniel documented it
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02:00:05_bilgus_think I've got it g#3264
02:01:52***Saving seen data "./dancer.seen"
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06:02:00***Saving seen data "./dancer.seen"
06:32:51speachy_bilgus_: so the fact that H10 somehow triggered this but not the ipods is sheer luck?
06:37:49speachyand this can be attributed to the compiler mis-optimizing things?
06:56:29speachyI confess I don't understand what you're trying to accomplush on L262-263; what's the point of reading the value if you're just going to set all bits except for the DIRTY bit anyway?
06:59:25speachyit seems the only practical difference is that you're setting addresss for each cacheline to all 1s
07:00
07:26:44_bilgus_speachy the address doesn't matter as far as not crashing but those unused bits I suspect
07:26:50_bilgus_'unused'
07:27:14_bilgus_but which ones bit 21 or bit 24-31??
07:27:59_bilgus_I also didn't appear to need to clear the dirty bit as they all 'SHOULD BE' valid once they get to me
07:28:08_bilgus_buttt.......
07:52:22speachywe don't want them marked dirty going to invalid addresses. I don't know how the CPU would handle that
08:00
08:02:01***No seen item changed, no save performed.
08:03:10_bilgus_I'm going to try and dump the status register now and figure out what those unused bits are coming through as
08:13:21speachyyeah. still strange how this only seems to screw upthe H10
08:13:37speachyis there something else special about it vs the ipods? RAM size?
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08:15:38_bilgus_ffff009f so it normally has the upper filled with ones
08:16:07_bilgus_I think they are both 32 bit but I wonder how much is silent corruption
08:16:13_bilgus_32 MB
08:16:29*speachy nods.
08:25:26speachyas an aside, I know one of the designers of the ARM7TDMI core.
08:33:52_bilgus_of I guess i read that backwards out of the file LE right?
08:38:49_bilgus_but if that the case then later it has them filled
08:39:17_bilgus_maybe I better format the file output
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09:15:57_bilgus_Looks to me that the upper bits are always 0 and I don't see anything amiss in the data either maybe its still alignment fooling me??
09:20:43speachyif you did a printf on a 32-bit field (using #x) the output is BE for human consumption
09:20:48speachy%x
09:21:19speachyif you're looking at 4 one-byte %02x fields, then it's LE
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09:44:12_bilgus_I got it but whats odd is this last line 0x0xf0005ff0 0xC00000 000000 0x00C00000
09:45:47_bilgus_that is a zero address marked valid and dirty
09:47:20_bilgus_maybe instead of filling the cache by pulling addresses I should try filling it manually
09:49:42_bilgus_context https://pastebin.com/0skBQfLW
09:51:45_bilgus_another at 390 but marked valid and clean
09:51:51_bilgus_weirrrdd
09:52:19_bilgus_those should be either filled or that 20 bit 1FFFF
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10:02:05***Saving seen data "./dancer.seen"
10:02:55speachyso to refill the cache just do what we did with the init code?
10:03:28speachyso that last entry is odd, yeah
10:03:42speachy..well, 0 _is_ technically a valid address
10:06:40_bilgus_yeah but we init off of 0x2000
10:07:06_bilgus_was 0x1000 your patch doesn't matter but who wuld be putting it in there an ISR?
10:07:34_bilgus_they are both odd but for different reasons
10:08:05_bilgus_actually i'm gonna try init with the code that invalidates it
10:08:13_bilgus_well pseudo invalidates it?
10:08:56speachyISR vector table starts at 0x0
10:09:54speachybut I don't see why that would ever get marked as dirty
10:10:11speachywell, unless we have a null pointer dereference + write somewhere.
10:16:11_bilgus_possible but why only here
10:21:10_bilgus_ok initializing it like we invalidate there are no longer any 0 addresses but I can't say that fixed it till I run it like 10 more times to be sure
10:23:54_bilgus_oddly I don't see any of the invalidated entries this run either
10:24:46braewoodsdoes armv4 not have a MMU?
10:25:15speachyarmv4 can have a MMU, but these specifically do not.
10:25:22braewoodsi see
10:25:39braewoodstoo bad, that might help with catching issues
10:26:21braewoodsan MMU to protect RB from being overwritten by user applications or so would be nice
10:27:35_bilgus_yeah this is kinda weird too I no longer see any invalidated entries through multiple runs
10:30:17_bilgus_well I guess I'm getting somewhere even with code size changes it hasn't crashed
10:30:30_bilgus_BBL
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12:02:09***Saving seen data "./dancer.seen"
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12:49:20braewoodsspeachy: how fast is the sequential read speed on your fiio m3k?
12:49:29braewoodsnot sure how fast the newer players are
12:49:39speachyno clue
12:49:50braewoodsoh i see
12:50:01braewoodsi usually benchmark my units to get an idea of how fast they are under the best circumstances
12:50:32braewoodsi've never seen higher than 13MB/s, i saw that in H120s and HDD1630s that were CF modded
12:50:45braewoodsjust weird seeing stuff slower than that
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