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#rockbox log for 2021-06-27

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07:42:48desowinI cannot get any more startup glitches now
07:43:42braewoodsdesowin: try harder! they must still be there! :P
07:45:02desowinwell, atleast the ones with >1% probability are not there anymore
07:46:19desowintoo bad the OF takes around 5 seconds before exploit kicking in, as it severly slows down on/off tests
07:47:02braewoodsgigabeat S is in a similar boat with OF dual boot support
07:47:05desowinUSB seems to fail when I pass the device to vmware image when the USB HID is enabled. Disabling USB HID solves the issue.
07:47:32desowinwell, workaround the issue, is more appropriate
07:47:35braewoodswell passthrough to virtual machines is unlikely to be something actual users will do
07:47:47braewoodsi'd be more concerned if it was a problem on real hardware
07:48:22desowinthat's reproducible way to get the CPPI handling code going nuts, so I would consider it to be a problem with the driver
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11:18:54braewoods g#3510
11:18:56rb-bluebotGerrit review #3510 at : mkzenboot: fix implicit function warning by James Buren
11:18:57braewoods g#3511
11:18:58rb-bluebotGerrit review #3511 at : rbspeex: fix shared linkage on newer Linux distributions by James Buren
11:19:21braewoodswhoever feels like reviewing this simple fixes
11:19:59braewoodsMarcAndersen: i found the cause of rbspeex failing to build. thanks for the report.
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12:14:08MarcAndersenbraewoods: Thanks for the rbspeex fix
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12:24:12MarcAndersenIs there a way to exclude some rock plugins from a build? I have problems with calculator.c in a windows sim, something about a definition of strtod.
12:25:45 Join hombrelaser [0] (
12:26:11braewoodsMarcAndersen: do you have the exact log output?
12:26:31MarcAndersenI will pull a fresh git and try again.
12:27:03hombrelaserHello, I'm planning on installing 128 gb on my ipod 5th gen with an iFlash adapter. Is it necessary for the iPod to have been "restored" by itunes to first use Rockbox or can I install rockbox after installing the iflash adapter?
12:28:47braewoodshombrelaser: i don't know the ipod ports but most targets require an OF reinstall when replacing the storage. it varies heavily though.
12:29:45braewoodsthere's some where the OF isn't needed; in any case it does need to be formatted in whatever manner the OF expects since rockbox usually piggy backs off of the OF bootloader
12:30:15hombrelaserOh, so the important part of the OF installation is the bootloader
12:30:46braewoodsyes, depends heavily though. on most PP targets the OF doesn't actually have to be present. you can just install the RB bootloader on the disk as is.
12:31:29braewoodsi think it's save to assume that it's needed here though.
12:31:33hombrelaserSo you recommend me trying rockbox the moment I install the drive or it's better to be safe and install the OF?
12:31:54hombrelaserOh I see, I'll see what can I do, I don't have access to a w10 pc at the moment
12:31:56*braewoods shrugs.
12:32:01braewoodsapple tends to be very weird and specific.
12:32:27braewoodsmost other mp3 players of the same era just expected a simple layout but not ipods last i checked
12:32:56braewoodsmeaning, single partition formatted with FAT32, type c partition
12:33:50braewoodslinux doesn't care about the partition type code but most other proprietary systems do
12:34:07braewoodsrockbox doesn't care either
12:48:09MarcAndersenIt's building now
12:57:35MarcAndersenHere is a log:
12:58:10braewoodsas i thought.
13:02:07***Saving seen data "./dancer.seen"
13:02:43braewoodsMarcAndersen: you can workaround it for now by removing strtod function from the source code
13:03:06MarcAndersenfrom calculator.c?
13:03:21braewoodsit's there because native targets lack strtod
13:04:03braewoodsit needs to be conditionally included
13:04:11braewoodsbut not sure how that should be done
13:04:30MarcAndersenSo if I do that I can't build native anymore? Isn't there a way to skip plugins?
13:04:53*braewoods sighs.
13:05:29braewoodsyou can always restore it via a git reset
13:05:38MarcAndersenThe calculator doesn't have speech anyway, but that would infact be a nice thing to have
13:08:27desowinMarcAndersen: actually, the chances are you'll be able to install rockbox on sansa connect without sighted assistance
13:09:10desowinthe only potential problem is if you have device with bootlaoder that for some reason is not working with the exploit, then you'd be stuck in recovery mode
13:09:26desowinto get out of recovery mode, OF needs to be loaded if that's the case
13:10:06desowinso if you wish to proceed, then backup any files you have on the device and press and hold power button for 10 seconds
13:11:25MarcAndersenAnother error:
13:11:49desowinthen press and hold the button on the right slightly above the wheel, hold volume up button (upper button on the left) and press power button
13:12:29desowinthe volume up and right button have to be held, power needs to be pressed and shortly released
13:12:43MarcAndersenI'm not with the device right now
13:13:50desowinare you building this on windows in mingw?
13:14:08MarcAndersenNo, I'm building a simulator
13:14:42MarcAndersenBut now I have this mikmod error
13:15:50MarcAndersenI can't use rockboy anyway
13:15:53desowinis this on ubuntu?
13:17:14desowinbut why mingw is being included? Are you targetting windows?
13:17:29MarcAndersenYes. I'm building a windows simulator
13:35:34 Quit amachronic (Ping timeout: 265 seconds)
13:38:09MarcAndersenCan you reproduce it?
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14:31:05desowinthe virtual machine pass through might not be a bug in sansa connect usb driver after all
14:31:29desowinthis issue happens only if it is connected via (cheap) usb hub
14:31:53desowinif connected directly, everything works fine
14:32:39desowinwhen the issue happens, with OpenVizsla I can see that the device really gets everything that was actually sent on the bus
14:34:01desowinthere's some IN tokens being sent to non-existent device, and also I can see split starts for other ports
14:34:53desowinI am not sure if the spec even allows to broadcast the split start to all hub downstream ports that have high-speed device connected
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14:50:36desowinwhen connected to docking station everything works fine, and so does when connected to decent usb hub
14:51:57braewoodsdesowin: ryzen host?
14:53:43desowinno, intel i9
14:54:34desowinbut I odubt host has anything to do with it, it just looks like the cheap hub is indeed cheap
15:02:08***Saving seen data "./dancer.seen"
15:04:22braewoodsok, ryzen hosts have a known issue with USB currently
15:13:46 Quit advcomp2019_ (Ping timeout: 268 seconds)
16:18:17amachronicdconrad: I saw your post, it does look like memory is being mapped wrongly.
16:18:39dconradgreat! well, not great, but y'know
16:19:18 Quit f1refly (Quit: see ya in hell)
16:19:29dconradI'm afraid I really don't know what I'm doing with stuff this low-level
16:19:36amachronicthose numbers being little endian... it seems there's something happening around 1k in size
16:20:26amachronichmm lemme check the remappings
16:20:49dconradthat pattern is repeatable too, except it appears that the 00 xx 00 00 values skip, but the xx 00 00 00 and 00 00 xx 00 values don't, if that makes any sense
16:23:01amachronicwell, you see the REG_DDRC_REMAP settings in spl-x1000.c?
16:23:21amachronicI think those control the mapping of physical addresses on the AHB bus to the DRAM
16:23:39amachronicthe ones for 32M RAM size might be wrong since I had to pull them out in a odd way
16:23:47dconradI see
16:23:47amachronictry this
16:24:13amachronicfor some reason they encoded the remapping as a loop instead of straight setting of registers.
16:24:23amachronicso I had to decompile the loop and run it to figure out the values
16:25:14MarcAndersenIs there a fix for my previous error with mikmod?
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16:26:01dconradI'll give it a shot!
16:26:23dconradthough I am curious how you get to those values
16:26:35amachronicI'm not sure what to expect, but this is the default mapping which should be 1 to 1 between bus and memory
16:26:37dconrador, rather what they do
16:27:10amachronicsee section 9.2.9 of x1000 manual
16:28:41dconradIt appears to have had no impact?
16:28:49dconradI'll have to look a little closer
16:29:28dconradmaybe I have the SPL_DDR_MEMORYSIZE somehow defined wrong
16:31:23dconradyeah somehow that didn't have an effect at all
16:31:42amachronicokaay... I'm not sure what's happening here.
16:31:51dconrad... I'm going to eliminate the #ifdef stuff just as a sanity check
16:32:06amachronicthe remapping passes through the lower 12 bits (= 4k pages)
16:32:22amachronicbut you seem to have a "periodic" pattern which is 1k in size?
16:33:08dconradyeah, here let me upload the .bin
16:33:28amachronictry halving the loop iteration count until the effect goes away">
16:35:49dconradand I'll do that
16:42:37amachronicthis one might be faster
16:44:03dconradI'll try it, same expected output?
16:44:29amachronicwell, the idea is write two different values 1kb apart and see what comes of it.
16:44:52amachronicthis should be unaffected by the remapping bits
16:45:46amachronicwhat I don't get, in your dump you _should_ see "xx 00 00 00" with xx ranging from 00h to FFh in the first 1kb
16:46:00amachronicbut instead you see "xx 01 00 00"
16:46:44amachronicthe next 1kb from offset 400h is right but then from 800h it's wrong again
16:48:28dconradah, I'll upload the new file, but I get 0xbb in both addr 0 and addr 00000400
16:48:47dconradso, it overwrote it in addr 0?
16:49:07amachronicyeah that's what I was afraid of
16:49:09dconradbut no other addresses are written to
16:49:12amachronictry swapping the order of the writes
16:49:36amachronicthe results should be the same but with 0xaa in both addrs
16:50:46dconradyou got it, exactly
16:51:02dconradhow on earth...
16:51:29amachronicI'm looking at REG_DDRC_MMAP
16:51:47amachronictry using the values from the 64M version
16:51:50amachronickeep the rest the same
16:52:53amachronic(this is totally arbitrary −− I am having a hard time understanding the manual to understand why the current value would be wrong)
16:54:28dconradyeah, looks like it had no effect
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17:00:14dconradin fact, I can use the 64k versions of both MMAP and REMAP registers and I get the exact same results
17:00:39amachronicyeah because they're only dealing with the upper bits of the address
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17:02:11***Saving seen data "./dancer.seen"
17:02:12amachroniccrap, maybe it's because of REG_DDRC_CFG
17:02:41amachronicDDR controller > register definition > DCFG (9.2.2)
17:04:51amachronicor maybe not... I thought maybe the CS bits were set for two RAM chips but it looks like only one is set
17:05:36dconradcould it be Data width 32-bit vs 16-bit?
17:05:52dconradno, we're dealing with addressing rather than data, huh
17:06:49amachronicbtw there's a datasheet for the DRAM here
17:07:20amachronicunfortunately I'm not too familiar with any of this either
17:09:15dconradhuh... come to think of it, I don't remember seeing a chip I would identify as RAM?
17:09:54amachronicI assume it's all in the chip package. sometimes the packaging can be melted off and there's a mini-PCB inside
17:10:14dconraddang, I had no idea
17:10:17amachronicnot something I've done myself, but I've seen pictures of it
17:13:55 Quit lebellium (Quit: Leaving)
17:14:57amachronicwell maybe this is a clue:
17:15:02amachronic"Each 67,108,864 bits bank is organized as 8,192 rows by 512 columns by 16 bits"
17:15:16amachronicand 16 bits * 512 columns = 8192 bits = 1024 bytes
17:15:35dconradaccessing data... in a 2d table?
17:15:57dconraddo we have the wrong row/column values?
17:21:46amachronicit's DCFG.COL0
17:22:05amachroniccol0 = 2 = 10 bit column address
17:22:19amachronicthe 32M chip has 9 bit column addresess
17:23:15dconradwhat's our label for that, REG_DDRC_CFG?
17:23:38amachronic(it was pretty silly of me to be renaming registers like this, in retrospect)
17:23:49*amachronic shrugs
17:23:54dconradah well
17:24:06dconradlooks like it's set in 3 places for some reason?
17:25:16amachronicwell I hope I calculated this right... change 0xa468a6c -> 0xa46896c and 0xa468aec -> 0xa4689ec
17:27:20dconradok, I was going to see if I could verify the values but I'll just give it a try
17:27:38dconrad(at work, we tend to use straight binary values, and now I see why...)
17:28:39amachronicwell, even better to use human readable names
17:28:57dconradyeah, but who wants to type all that in? :-P
17:29:24amachronic... I just didn't bother because I figured, "who's ever going to have to touch this again?"
17:29:28dconradok, cross your fingers
17:31:01dconrad0xAA in 0, and 0xBB in 400
17:31:18dconradlet me try the sequential values test now...
17:31:24dconrad(btw, good job!!!)
17:32:17amachronicalright! seems like you might be getting somewhere
17:32:57dconradI'm thinking... I might work on making the registers human-readable with defines, I'm good at that kind of systematic stuff
17:33:06amachronicI already have a system for that
17:33:07dconradwell, later
17:33:11dconradto do that
17:33:26dconradI see!
17:33:55amachronicThe rest of the codebase uses this, that's where all the jz_writef magic comes from.
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17:35:27dconradyeah, the sequential stuff looks correct now, let me upload a .bin just for fun">
17:37:21dconradnow... I think the next step is just to go ahead and see if I can get das blinken lightsen on the 2nd stage
17:37:46dconradweird how the 1st stage seemed unaffected by this though
17:38:41amachronicif you update the reggen files, this script may help
17:39:35dconradaha, the bootloader upload now flashes!
17:40:00dconradok, sweet!
17:40:41amachronicthe 1st stage SPL is not affected, btw, because it doesn't run from DRAM.
17:41:11amachronicit runs from a 16k on-chip SRAM (maybe part of the l2 cache?)
17:42:04dconradI see, is that kind of the whole reason there's 2 stages anyway?
17:42:19amachronicpretty much.
17:44:16amachronicthe question is now, how far does rockbox get? (just for kicks)
17:44:49dconradhah, well if I add spl_error() to the beginning of system_init(), I get a flashing backlight, but if I remove it, I get nothing
17:45:03dconradso I'm still hanging somewhere
17:45:08dconradbut, after that point
17:46:59amachronicall you can do is keep bisecting until you locate the problem
17:47:35dconradwell, it's nice to have a systematic way to debug it though for sure
17:48:07dconradso does that DDR CFG register now need to be set differently for 32 vs 64m targets as well?
17:48:42amachronicI guess that extra bit is what makes the difference between 32m and 64m
17:49:12dconradweird that they would actually change the number of addressing bits though
17:49:36dconradthat seems like a fundamental thing
17:51:21dconradwell, we're getting through system_init() ok, so... just gotta keep going
17:52:29amachronicLCD is the most likely flaky part
17:56:23dconradyup, no surprise there
17:56:32dconradwe can't get through lcd_init();
17:57:06braewoods_bilgus: think i'm going to redesign my ZIP approach. i realized that i should probably cache the CD table to reduce how much seeking i have to do. otherwise it'll probably kill performance jumping around all over the file.
18:00:38amachronicdconrad: try setting LCD_CONTROL pingroup bits 0x1f instead of 0x1a
18:01:28amachronicit's 0x1a on the m3k because those other pins need to be controlled manually as part of the reset sequence
18:02:01amachronicwhich makes me wonder, is it true that the erosq doesn't need to do a similar thing?
18:02:38dconradwas that in the lcd init functions in the m3k's OF?
18:03:13amachronicyeah it's supposed to be the chip select pin
18:03:43dconradwell, no change using 0x1f unfortunately
18:04:15 Quit aquijoule_ (Remote host closed the connection)
18:05:08amachronicodd, it shouldn't hang, even if everything goes horribly wrong. It's only DMAs out of memory so at worst the LCD gets scrambled garbage, but the rest of the system should be ok.
18:06:56amachronicunless the LCD never acks which could very well cause a hang. in which case, it should hang at lcd_tgt_enable() but not before.
18:09:14dconradhah, you got it
18:09:19dconradon down the rabbit hole we go
18:12:38dconradyep, it hangs when calling the lcd_cmd_enable[] commands
18:13:03dconrad... who'd have seen that coming???
18:13:34amachronicso it'd appear (1) your LCD module is not init'd or (2) maybe the CS pin level is wrong
18:14:17amachronicPB18 is supposed to be the chip select pin
18:14:30dconraddoes the hardware not take care of the chip select automatically? guess not...
18:15:08amachronicit does when you assign it to the GPIOF_DEVICE function but who knows what it actually does? they don't actually document this...
18:15:41dconradturns out, if you want someone to use your processors, you have to write down how they work, lol
18:16:42amachronic...and who needs to know how they work when the vendor provides a magic kernel blob?
18:16:58dconradwell, yeah that's it isn't it
18:17:27dconradso LCD_CE is chip select, right? what's RD?
18:18:11amachronicRD is a read signal, it's not used because the HW has no way to read data from the panel
18:18:18dconradok, sweet
18:18:44amachronicso the M3K keeps it high (which is the inactive level)
18:25:21dconrad... I just kinda aped the lcd_set_clock() call from the m3k and we got through the lcd_exec_commands() call!
18:26:00amachronicah, well that was obvious
18:26:09dconradyeah, in retrospect
18:26:21amachronicI can't believe I missed that.
18:27:07dconradI guess I was confused and thought it was covered by the EXTC (external clock?) commands in the command set, but that's a completely different thing isn't it
18:27:40amachronicalright, I knew you posted this
18:27:49amachronicyour raw "pixclock" is 0xC350
18:28:07amachronicthat's convertible to a clock frequency but you have to chase down the KHZ2PICOS macro and undo it
18:28:42amachronic(at least I think that's what the macro is called.)
18:29:28amachronicwhich is... 20,000 khz
18:29:53dconradcan I not set it directly with this X1000_CLK_SCLK_A call?
18:30:17dconrador, 20mhz is the value to put in there
18:30:48dconradI see
18:31:19amachronicSCLK_A is the clock source, which is actually just APLL
18:31:45amachronicyour other option is MPLL, but right now Rockbox is set up to not use it
18:42:36dconradlooks like now it can't get through show_logo(), which makes sense if the lcd isn't initialized properly
18:42:49dconradthough I'm confused why the backlight isn't at least coming on
18:43:12dconrad... though maybe I should put this down and go eat some supper
18:43:50dconradamachronic, thanks a bunch for helping me!
18:44:53dconrad...oh, the backlight is initialized farther down, that's why
18:51:20amachronicdconrad: no problem. I should probably be going myself though.
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19:48:17 Quit MarcAndersen (Quit: I was using NightOwl 0.2.)
19:53:35 Quit MarcAndersen_ (Quit: Miranda NG! Smaller, Faster, Easier.
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21:22:33*MarcAndersen slaps MarcAndersen around a bit with a large trout
21:26:17__builtinis logf() thread-safe?
21:27:08 Join jadzia [0] (
21:36:02__builtin... evidently no
22:15:33__builtinthe rabbit hole of quake really is quite deep
22:16:03__builtinI've been hunting this one heisenbug for days now, and it's looking like it originates within a call to lseek (!?)
22:17:18__builtinwell, fseek(), rather
22:38:25__builtinaaand I'll be damned: it was a stack overflow silently thrashing nearby portions of memory
22:38:33__builtin(in a worker thread)
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22:41:49 Quit richbridger (Ping timeout: 268 seconds)
22:51:58rb-bluebotBuild Server message: New build round started. Revision d1a92aafff, 297 builds, 8 clients.
22:52:20__builtin... and there goes my first commit in 6 months :)
23:02:17***Saving seen data "./dancer.seen"
23:04:38rb-bluebotBuild Server message: Build round completed after 761 seconds.
23:04:42rb-bluebotBuild Server message: Revision d1a92aafff result: All green
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23:56:52__builtindo we have an organization set up with libera yet?

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