From: Andrew Jamieson <ajamiesn_at_mira.net>
Date: Sun, 9 Dec 2001 22:42:52 +1100

Hi.

For my sins, I'm the guy who is hoping to give you software ppl an idea of how the insides of the AJB are connected. Now, before I start hacking away at my precious AJB, I'm making a preliminary schematic based only on visuals from the various pictures one can get on the net. This may sound dodgy, but it is easier to 'buzz-out' a circuit with a multimeter if one has a vauge idea of how things should be connected in the first place. Alot of connections are common sense anyway. In the interests of speeding things along (getting a complete schematic of the AJB may take a few weeks ...) I will keep you all up to speed on progress as I go.

Now Bjorn has asked if I can give the CS mapping first. Well some things are obvious from the outset, and some I can make fairly well educated guesses on. Do bear in mind, tho, that this is all derived from looking at the datasheets and pictures of the PCBs - time will tell how acurate I am in my estimations.

CS1: This _must_ be used with the DRAM, as this is the only way the SH-1 supports direct DRAM attachment (pg 142 datasheet).

CS0: I have a feeling that this is used to interface to the FLASH, but this would cause problems with the SH-1 spec, as this area should only be usable for either internal ROM only, or external ROM only - and they advise against switching on the fly. The other contenders for the CS of the FLASH at the moment are; CS2, CS4, & CS6. There is something interesting happening with the mode select pins too, but I will leave conjecturing until I have measured them.

CS2/CS4: I would guess that either of these are used for the LCD interface, which appears to be a standard 8 bit LCD Chip On Glass controller. Once I know the exact pinout, I should be able to guess at the exact chip used.

Other stuff:

* Dispite what I originally thought, the SH-1 has a direct interface to the HD, using buffers to cut off the HD bus when the ISD-200 wants to drive the disk. So there is probably another CS that is used for HD access.

* I am still certain that there must be a SW I2C interface used to control the two MAS chips, and possibly get info from the ISD. This would be done with port pins, probably from port B.

* All of the A/D inputs head off somewhere ... god knows what they are used for at this stage.

That's all for now. I include a PDF of the schematic so far, I know how even a bit of a circuit diagram can help in the deciphering of assembler. I am fairly confident that not too much is wrong, even at this early stage.

One thing: I don't really want archos personel seeing schematics of thier products on the web, at least not ones that will lead back to me, so if you could keep them from linkable sites, that would be appriciated. I am actually really enjoying doing this, and have no problem sharing the info with a closed user group for such a good cause (I will place my request for no pause between songs now ;), I just don't want a letter from Archos lawyers.

CM
Received on 2001-12-09