From: Daniel Stenberg <daniel_at_haxx.se>
Date: Wed, 9 Jan 2002 17:26:44 +0100 (MET)

On Wed, 9 Jan 2002, Nielsen Linus (ext) wrote:

> > Well... Won't re-engineering the code offer any clues?
>
> Of course it will. Feel free to do it... :-)

I intend to. I just ventilate my thoughts here to verify that my thinking
isn't entirely wrong.

> The IDE seems to use plain parallel I/O.

What is this assumption based on?

> The serial line is probably using some kind of DMA, or the CPU would not
> keep up with the speed of data. Or it may have a huge FIFO which is filled
> by the CPU once in a while.

The DMA registers (according to the SH-1 harware manual) are:

 Source SAR0-SAR3
 Destination DAR0-DAR3
 Transfer count TCR0-TCR3
 Channel control CHCR0-CHCR3
 Operation register DMAOR

All these registers are memory-mapped in the CPU, aren't they? Do we know
where and if so, do we have any list like the above that can be filled in
with the address the register is found on in the Archos? It would make it
easier to read the assembler...

-- 
  Daniel Stenberg -- Dissecting Archos => http://bjorn.haxx.se/jukebox/

Received on 2002-01-09