Rockbox mail archive
Subject: Re: RAM limit
From: Matthias Wächter (matthias_at_waechter.wiz.at)
On Mon, 12 Aug 2002, Linus Nielsen Feltzing wrote:
> > I mean, we all know that 2MB is not _that_ much (f.e. for 200+ song
> > titles in the list to sort :-)), other players have 8MB to save
> > battery power (well, to make the device smaller by using smaller
> > batteries). The SH-1 supports up to 16 MB of DRAM, so even if it's
> > a hard and dirty job, one could enhance/replace the memory using
> > additional DRAM modules (f.e. by piggy-packing them on the one
> > already there). An additional address decoder will be necessary,
> > too.
> Then you need another DRAM controller as well, since the DRAM
> controller and address decoder is internal to the SH1.
There are two alternatives:
a) Remove the existing chip (1M x 16) and replace it with a larger chip
(4M x 16). In theory this should work (and by wiring two additional
address lines). In practice, this is nearly impossible for two reasons:
(1) I can't find a manufacturer offering 4M x 16 devices for 5V (maybe I
don't search correctly), (2) I can't find a manufacturer offering any FPM
(fast page mode) DRAM in this size after all (The main age for these chips
was about 1996-1998). Maybe we find some old PS/2-SIMMs we can unsolder
the parts from, but I don't think we will succeed in making something
'easy' and 'for longer times available' to help all Archie-owners
upgrading their devices. Maybe, if the SH1 was a 3.3V component, we
could've found a replacement chip (for 3.3V there are a lot of
manufacturers for 4M x 16 FP-DRAM, maybe one of them has some spare
devices for us), but currently we would need at least 2 x 16bit voltage
translators 3.3V <-> 5V to connect those chips into the Archos. What a
mess would that be! Even if the chip were pin-compatible to the current
1Mx16 chip, we would have to wire all the pin elsewhere.
b) Add additional 1M x 16 chip(s) plus an address decoder. Problem here is
that we get a lot of additional heat (about 0.3 W per memory chip), and
additional heat from the address decoder (about 0.6 W!), which we would
have to put into a GAL. All this not accounting for the additional space
needed for all this. With a clever address decoder design, you can just
use the SH1 with its DRAM controller, though.
For example: While /RAS is asserted (falling edge), the extra address
lines A10,A11 are available to be decoded. One just has to 'gate' the
/CASL and /CASH to the decoded memory chip, the other chips just see a
/RAS access without a /CASx. I already wrote some lines of VHDL code for
the GALs, but I think this leeds us nowhere.
Slowly I think that project is a little bit too much for our little
Additional comments? For the chips we would at least need PS/2 SIMMs
with the following features:
a) 16 MB with 2 chips
b) 32 MB with 4 chips (2 chips per side).
the chips should have at least 44 pins each (that would make them 16-bit
chips). Maybe some of us have such SIMM modules in their old dusty
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Page was last modified "Jan 10 2012" The Rockbox Crew