From: Michael Sevakis <jethead71_at_sbcglobal.net>
Date: Wed, 16 May 2007 00:38:13 -0400

After some evaluation with your emulator I have some questions and observations.

1) CPU_HI_INT_EN (0x60004124 in our headers) is labelled at COP_INT_EN by your emulator. Do you know of a difference or is this a mislabelling? PP5024.h should be updated if there are some.

2) Which unnamed registers were you referring to? Which addresses? I do see other addresses being referenced near the *_INT_* range.

3) What's with bit 6 in CPU_HI_INT_STAT? How are you observing the setting of this because I certainly seem to be missing it unless setting it deliberately and so I'm unclear how you found it. The emu just sets bit 0 on the keys..

4) When bit 0 _is_ set in CPU_HI_INT_STAT, the regdump shows that the OF does in fact poll its GPIO ports at this point. I haven't check to see if it reads them on bit 6 set as well yet.

5) The OF check all 64 status bits on every timer interrupt and TIMER1_MASK is _not_ set when it receives 0x00000001/0x40000000 at least on the emu.

6) The keys do change bit 6 but I haven't any idea how to ack it when it's actually hot and hence the never ending interrupt. Perhaps leaving some things out in the dump is concealing something important.
  ----- Original Message -----
  From: Antonius Hellmann
  To: Michael Sevakis ; Rockbox development
  Sent: Tuesday, May 08, 2007 3:19 PM
  Subject: Re: Sansa (PP502x?) GPIO interrupts in rockbox software


  Yes, the CPU/COP_INT_EN are write only to my understanding. The results of these operations can be evaluated in the CPU/COP_INT_EN_STAT. I have no idea, why on the PP5020 this doesn't work. What I also don't understand is, that beside CPU-/COP-registers there is a third group of unnamed registers (INT_STAT etc).
  Did you recognize, that there are at least three (may be more) different assembler instructions to set some
  groups in the cpsr data? Also interesting fact in the original sansa code is, that they sometimes stack the spsr register in the interrupt context, probably allowing interrupts in interrupt contexts.

  Yes, I did the same dump for the cpu interrupts, which did not show any anomalies.
  And yes, CPSRs have to be completely independent between COP and CPU, otherwise .... garbage.

  The keys definitely change the HI_INT_STAT bit6. So if someone wants to implement key/scrollwheel interrupt handling, the bit6 in the CPU-/COP_HI_INT_EN register should do it.
Received on 2007-05-16