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Subject: Re: Power Efficiency Tradeoffs

Re: Power Efficiency Tradeoffs

From: Catalin Patulea <>
Date: Mon, 31 Mar 2008 02:22:01 -0400

Hi everyone,

Sorry to wake up an ancient thread -- I've had a bit more time to
think about your comments.

Indeed, there is a non-zero static power dissipation at f = 0. I will
assume it's constant for a given voltage. In addition, a fairly good
approximation is that power increases linearly with frequency (not
quadratically; it does that with voltage). So power for a chip can be
roughly written as:
P = P0 + Ps*f
where P0 is the static power in W and Ps is the "switching" power in W/Hz.

Once again, for the entire discussion, we take core voltage to be constant.

Together with my previous assumption that time required to carry out a
given task is exactly inversely proportional to the frequency, we can
define a constant W of a given task that is the amount of work
required for it. This is unitless because it's seconds * Hertz.

So, the total amount of energy required for the task is:
E = P * t
   = P0*t + Ps*f*t
And since t = W/f,
E = P0*W/f + Ps*W

Now, we are looking to minimize the energy needed for a particular
task by varying frequency and only frequency (we assume the target
architecture does not automatically change voltage along with
frequency, which I believe is a reasonable assumption for the
medium-range hardware targeted by Rockbox). So we set the first
derivative of E to 0:

dE/df = 0
-P0*W/(f^2) = 0

What does this mean? Energy is at a minimum when f tends toward infinity.

This even makes sense intuitively: as frequency increases, the
contribution of the Ps term become large enough to cancel out the P0
term. In other words, the task is executed so fast that the static
power doesn't "have enough time to matter".

Okay, so that was a lot of text to make one point. Thoughts?

In intend to actually try this with a PIC microcontroller at some point.


On Mon, Jan 21, 2008 at 6:43 PM, Bertrik Sikken <> wrote:
> Burelli Luca wrote:
> >
> > On Sat, 12 Jan 2008, Catalin Patulea wrote:
> >
> >> - I believe (correct me if I'm wrong) that, in general, power
> >> consumption is proportional to the core frequency. Let the power
> >> consumptions of the cores be P_1 = k*f_1 and P_2 = k*f_2.
> >
> > An accurate estimation of power consumption in digital electronics is
> > not so easy to figure out. However, as a rule of thumb, you may assume
> > there's a constant power dissipation which is due to leakage (non-ideal
> > switches allowing current to flow even where and when it should not),
> > and a "dynamic" power dissipation that is proportional to Vdd (the
> > switching voltage) and to _the square_ of the switching frequency. So
> > the above would be better written as P_1 = P_{1,leak} + k * f_1^2,
> > meaning that if you run the CPU twice as fast, you need four times the
> > energy (ignoring leakage). That's why clock throttling helps _a lot_ in
> > reducing battery drain!
> >
> > Hope I remembered things correctly from my University classes :-)
> I think you have the relations mixed up.
> In one clock tick, a bunch of internal nodes acting as tiny capacitors
> need to be charged or discharged, dissipating an amount of energy equal
> to the energy contained in those capacitors.
> A charged capacitor C has energy E = 1/2 * C * V * V, which demonstrates
> the quadratic relation between voltage and consumed dynamic power.
> Increasing the clock simply means that this happens more often each
> second, which points to a linear relation between frequency and
> dynamic power.
> Kind regards,
> Bertrik
Received on 2008-03-31

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