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Subject: Re: PP502x cache bug and ATA DMA test build

Re: PP502x cache bug and ATA DMA test build

From: Boris Gjenero <>
Date: Sat, 04 Feb 2012 13:28:22 -0500

On 03/02/2012 8:43 PM, Michael Sevakis wrote:
> For H10 20GB, dircache init and database init seem to pass alright where
> as before with DMA it would fault frequently. It's running UDMA 2.

Thanks for testing. It's nice to see that DMA is working better now.

UDMA 2 is the maximum set at compile time because that's the fastest
mode that works at 30 MHz. UDMA 4 can work at 80 MHz, but at least with
MK3008GAL, it's not really helpful. (In even UDMA 1 at 24
MHz is very close to the drive's top read speed.)

In the OF, it seems DMA is only used at 80 MHz. When I first started
investigating the DMA problems, I thought that use of DMA at 30 MHz or
changing of boost state during DMA could be responsible for instability.
However, according to my tests, UDMA 2 seems totally stable at 30 MHz
and when changing between 30 and 80 MHz during DMA.

Best regards,

Received on 2012-02-04

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