Index: firmware/export/as3525.h =================================================================== --- firmware/export/as3525.h (revision 20492) +++ firmware/export/as3525.h (working copy) @@ -26,10 +26,13 @@ #define ECCSIZE 512 #define ECCBYTES 3 +/* AS352X MMU Page Table Entries */ +#define TTB_SIZE 0xfff /* Mimic OF */ +#define TTB_BASE_ADDR 0x307fc000 /*Mimic OF */ + /* AS352X device base addresses */ - /* ------------------------------------------------------------------------ * AS352X Registers Index: firmware/SOURCES =================================================================== --- firmware/SOURCES (revision 20492) +++ firmware/SOURCES (working copy) @@ -266,9 +266,9 @@ drivers/isp1583.c #endif #else /* !defined(HAVE_USBSTACK) */ -#if CONFIG_USBOTG == USBOTG_ISP1362 +#if CONFIG_USBOTG == USBOTG_ISP1362 drivers/isp1362.c -#elif CONFIG_USBOTG == USBOTG_M5636 +#elif CONFIG_USBOTG == USBOTG_M5636 drivers/m5636.c #endif #endif /* !defined(HAVE_USBSTACK) */ @@ -341,7 +341,7 @@ target/arm/i2c-pp.c #elif CONFIG_I2C == I2C_PNX0101 target/arm/pnx0101/i2c-pnx0101.c -#elif CONFIG_I2C == I2C_TCC780X || CONFIG_I2C == I2C_TCC77X +#elif CONFIG_I2C == I2C_TCC780X || CONFIG_I2C == I2C_TCC77X target/arm/i2c-telechips.c #elif CONFIG_I2C == I2C_S3C2440 /* no i2c driver yet */ @@ -457,7 +457,7 @@ target/sh/archos/ata-archos.c target/sh/archos/ata-as-archos.S target/sh/archos/lcd-archos-bitmap.c -target/sh/archos/lcd-as-archos-bitmap.S +target/sh/archos/lcd-as-archos-bitmap.S target/sh/archos/recorder/button-recorder.c target/sh/archos/recorder/power-recorder.c target/sh/archos/recorder/powermgmt-recorder.c @@ -1024,7 +1024,7 @@ target/arm/pnx0101/iriver-ifp7xx/lcd-ifp7xx.c target/arm/pnx0101/iriver-ifp7xx/power-ifp7xx.c target/arm/pnx0101/iriver-ifp7xx/powermgmt-ifp7xx.c -target/arm/pnx0101/iriver-ifp7xx/usb-ifp7xx.c +target/arm/pnx0101/iriver-ifp7xx/usb-ifp7xx.c #ifndef BOOTLOADER target/arm/pnx0101/pcm-pnx0101.c #endif /* BOOTLOADER */ @@ -1107,6 +1107,7 @@ #ifdef SANSA_E200V2 #ifndef SIMULATOR +target/arm/mmu-arm.S target/arm/as3525/sansa-e200v2/lcd-e200v2.c target/arm/as3525/sansa-e200v2/button-e200v2.c target/arm/as3525/backlight-e200v2-fuze.c Index: firmware/target/arm/mmu-arm.h =================================================================== --- firmware/target/arm/mmu-arm.h (revision 20492) +++ firmware/target/arm/mmu-arm.h (working copy) @@ -53,6 +53,10 @@ /* will do writeback */ void invalidate_idcache(void); +#if CONFIG_CPU==AS3525 && !defined(BOOTLOADER) +void as3525_mmu_init(void); +#endif /*CONFIG_CPU==AS3525 && !defined(BOOTLOADER) */ + #define HAVE_CPUCACHE_INVALIDATE #define HAVE_CPUCACHE_FLUSH Index: firmware/target/arm/crt0.S =================================================================== --- firmware/target/arm/crt0.S (revision 20492) +++ firmware/target/arm/crt0.S (working copy) @@ -87,6 +87,9 @@ ldrhi r5, [r2], #4 strhi r5, [r3], #4 bhi 1b + + bl as3525_mmu_init + #endif /* Initialise bss section to zero */ @@ -97,7 +100,7 @@ cmp r3, r2 strhi r4, [r2], #4 bhi 1b - + /* Set up some stack and munge it with 0xdeadbeef */ ldr sp, =stackend ldr r2, =stackbegin @@ -106,12 +109,12 @@ cmp sp, r2 strhi r3, [r2], #4 bhi 1b - - /* Set up stack for IRQ mode */ + + /* Set up stack for IRQ mode */ msr cpsr_c, #0xd2 ldr sp, =irq_stack - /* Set up stack for FIQ mode */ + /* Set up stack for FIQ mode */ msr cpsr_c, #0xd1 ldr sp, =fiq_stack @@ -148,7 +151,7 @@ b UIE data_abort_handler: - sub r0, lr, #8 + sub r0, lr, #8 mov r1, #2 b UIE Index: firmware/target/arm/as3525/debug-as3525.c =================================================================== --- firmware/target/arm/as3525/debug-as3525.c (revision 20492) +++ firmware/target/arm/as3525/debug-as3525.c (working copy) @@ -46,19 +46,154 @@ short button_dbop_data(void); #endif -static unsigned read_cp15 (void) +static unsigned read_cp15 (int reg) { unsigned value; + switch (reg) { + + case 0: /* Register 0 Op2 =0 ID Code */ + asm volatile ( + "mrc p15, 0, %0, c0, c0, 0 @ read control reg\n":"=r" + (value)::"memory" + ); + return (value); + case 1: /* Register 1 Control */ + asm volatile ( + "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n":"=r" + (value)::"memory" + ); + return (value); + case 2: /* Register 2 Translation Table Base */ + asm volatile ( + "mrc p15, 0, %0, c2, c0, 0 @ read control reg\n":"=r" + (value)::"memory" + ); + return (value); + case 3: /* Register 3 Domain Access Control */ + asm volatile ( + "mrc p15, 0, %0, c3, c0, 0 @ read control reg\n":"=r" + (value)::"memory" + ); + return (value); + case 4: /*Reg 5 Fault Status of prefetch*/ + asm volatile ( + "mrc p15, 0, %0, c5, c0, 1 @ read control reg\n":"=r" + (value)::"memory" + ); + return (value); + case 5: /* Register 5 Fault Status */ + asm volatile ( + "mrc p15, 0, %0, c5, c0, 0 @ read control reg\n":"=r" + (value)::"memory" + ); + return (value); + case 6: /* Register 6 Fault address */ + asm volatile ( + "mrc p15, 0, %0, c6, c0, 0 @ read control reg\n":"=r" + (value)::"memory" + ); + return (value); + case 7: /* Register 0 Op2 =1 Cache type */ + asm volatile ( + "mrc p15, 0, %0, c0, c0, 1 @ read control reg\n":"=r" + (value)::"memory" + ); + return (value); + case 8: /*Reg 9 Cache lockdown Op2 1=Icache*/ + asm volatile ( + "mrc p15, 0, %0, c9, c0, 1 @ read control reg\n":"=r" + (value)::"memory" + ); + return (value); + case 9: /*Reg 9 Cache lockdown Op2 0 = Dcache*/ + asm volatile ( + "mrc p15, 0, %0, c9, c0, 0 @ read control reg\n":"=r" + (value)::"memory" + ); + return (value); + case 10: /*Reg 10 TLB lockdown Op2 0 = Dcache*/ + asm volatile ( + "mrc p15, 0, %0, c10, c0, 0 @ read control reg\n":"=r" + (value)::"memory" + ); + return (value); + case 11: /*Reg 10 TLB lockdown Op2 1=Icache*/ + asm volatile ( + "mrc p15, 0, %0, c10, c0, 1 @ read control reg\n":"=r" + (value)::"memory" + ); + return (value); + case 13: /* Register 13 FCSE PID */ + asm volatile ( + "mrc p15, 0, %0, c13, c0, 0 @ read control reg\n":"=r" + (value)::"memory" + ); + return (value); + case 15: /* Register 15 Test configuration */ + asm volatile ( + "mrc p15, 0, %0, c15, c0, 0 @ read control reg\n":"=r" + (value)::"memory" + ); + return (value); + return (0xdeadbeef); + } + return (0xdeadbeef); +} + +static unsigned read_ttb (int line) +{ + unsigned value; + asm volatile ( - "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n":"=r" - (value)::"memory" + "ldr r0, [r0] \n":"=r" + (value)::"memory" ); return (value); } bool __dbg_hw_info(void) { + char buf[50]; + int line; + + lcd_clear_display(); + lcd_setfont(FONT_SYSFIXED); + + while(1) + { + line = 0; + _DEBUG_PRINTF("[CP15 Registers:]"); + _DEBUG_PRINTF("c00 : 0x%8x ID", read_cp15(0)); + _DEBUG_PRINTF("c01 : 0x%8x CacheType", read_cp15(7)); + _DEBUG_PRINTF("c1 : 0x%8x Control", read_cp15(1)); + _DEBUG_PRINTF("c2 : 0x%8x TTB", read_cp15(2)); + _DEBUG_PRINTF("c3 : 0x%8x DomainCTL", read_cp15(3)); + _DEBUG_PRINTF("c50 : 0x%2x Data FSR", read_cp15(5)); + _DEBUG_PRINTF("c51 : 0x%2x Prefetch FSR", read_cp15(4)); + _DEBUG_PRINTF("c6 : 0x%8x FltAddress", read_cp15(6)); + _DEBUG_PRINTF("c90 : 0x%8x DcacheLock", read_cp15(9)); + _DEBUG_PRINTF("c91 : 0x%8x IcacheLock", read_cp15(8)); + _DEBUG_PRINTF("c100: 0x%8x TLBLockD", read_cp15(10)); + _DEBUG_PRINTF("c101: 0x%8x TLBLockI", read_cp15(11)); + _DEBUG_PRINTF("c13 : 0x%8x FCFE PID", read_cp15(13)); + _DEBUG_PRINTF("c15 : 0x%8x Test", read_cp15(15)); + line++; + _DEBUG_PRINTF("[TTB Lines]"); + + int ttbline=0xff9; + + while(ttbline <= 0xfff){ + _DEBUG_PRINTF("line 0x%4x : 0x%8x ", ttbline, + read_ttb((TTB_BASE_ADDR)+(ttbline*4))); + ttbline++; + } + + lcd_update(); + if (button_get_w_tmo(HZ/10) == (DEBUG_CANCEL|BUTTON_REL)) + break; + } + lcd_setfont(FONT_UI); return false; } @@ -84,8 +219,6 @@ _DEBUG_PRINTF("DBOP_DIN: %4x", button_dbop_data()); #endif line++; - _DEBUG_PRINTF("[CP15]"); - _DEBUG_PRINTF("CP15: 0x%8x", read_cp15()); lcd_update(); if (button_get_w_tmo(HZ/10) == (DEBUG_CANCEL|BUTTON_REL)) break; Index: firmware/target/arm/mmu-arm.S =================================================================== --- firmware/target/arm/mmu-arm.S (revision 20492) +++ firmware/target/arm/mmu-arm.S (working copy) @@ -80,7 +80,7 @@ dump_dcache_range: add r1, r0, r1 @ size -> end cmp r1, r0 @ end <= start? - bxls lr @ + bxls lr @ tst r0, #31 @ Check first line for bits set bicne r0, r0, #31 @ Clear low five bits (down) mcrne p15, 0, r0, c7, c14, 1 @ Clean and invalidate line by MVA @@ -132,7 +132,7 @@ mcr p15, 0, r0, c7, c10, 4 @ Data synchronization barrier bx lr @ .size invalidate_dcache, .-invalidate_dcache - + /* * Invalidate entire ICache and DCache * will do writeback @@ -190,18 +190,18 @@ @ 10: superuser - r/w, user - no access @ 4: should be "1" @ 3,2: Cache flags (flags (r3)) - @ 1: Section signature + @ 1: Section signature orr r0, r0, r3 orr r0, r0, #0x410 orr r0, r0, #0x2 - + @ unsigned int* ttbPtr = TTB_BASE + (va >> 20); - @ sections are 1MB size + @ sections are 1MB size mov r1, r1, lsr #20 ldr r3, =TTB_BASE_ADDR - add r1, r3, r1, lsl #0x2 - - @ Add MB to pa, flags are already present in pa, but addition + add r1, r3, r1, lsl #0x2 + + @ Add MB to pa, flags are already present in pa, but addition @ should not effect them @ @ for( ; mb>0; mb--, pa += (1 << 20)) @@ -427,7 +427,7 @@ adds r0, r0, #0x04000000 @ will wrap to zero at loop end bne 1b @ clean_start @ mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer - bx lr @ + bx lr @ .size clean_dcache, .-clean_dcache /* @@ -476,12 +476,73 @@ .type invalidate_idcache, %function .global cpucache_invalidate @ Alias invalidate_idcache: -cpucache_invalidate: +cpucache_invalidate: mov r1, lr @ save lr to r1, call uses r0 only bl invalidate_dcache @ Clean and invalidate entire DCache mcr p15, 0, r0, c7, c5, 0 @ Invalidate ICache (r0=0 from call) mov pc, r1 @ .size invalidate_idcache, .-invalidate_idcache + +#if CONFIG_CPU==AS3525 && !defined(BOOTLOADER) +/* Mimic OF initialization of the mmu and pagetable + * + *void as3525_mmu_init(void) + * + */ + + .section .text, "ax", %progbits + .align 2 + .global as3525_mmu_init + .type as3525_mmu_init, %function + + /* Disable Icache, Dcache, and MMU. Set Fast Bus. */ +as3525_mmu_init: + mrc 15, 0, r0, c1, cr0, 0 @ //Read control reg + bic r0, r0, #0x1 @ //Disable MMU + bic r0, r0, #0x4 @ //Dcache Disable + bic r0, r0, #0x1000 @ //Icache Disable + bic r0, r0, #0xc0000000 @ //Set Fast Bus + mcr 15, 0, r0, c1, c0, 0 @ //Make it so + + /* Set up ttb Base = TTB_BASE_ADDR and tags */ + /* build tags */ + mov r2, #0xc00 @ //Acc perm 11= r/w all + orr r2, r2, #0x0 @ //Domain = 0x0 + orr r2, r2, #0x10 @ //bit 4 should be 1 + orr r2, r2, #0x0 @ //Cache flags? + orr r2, r2, #0x2 @ //10= Section Type + @ // r2=0x00000c12 + ldr r1, =TTB_SIZE @ // oxfff=4095 decimal + ldr r0, =TTB_BASE_ADDR @//TTB Base Pointer + mcr 15, 0, r0, c2, c0, 0 @ //Write TTB reg + + /* Map each memory location to itself no cache */ +1: @ // 0xfff00c12 + orr r3, r2, r1, lsl#20 + str r3, [r0, r1, lsl#2] @ // Store tag in table + subs r1, r1, #0x1 @ // r1-- + bpl 1b @ // loop for r1>= 0 + + orr r3, r3, #0xc @ // r3=0x000000c1e + str r3, [r0] @ //1MB sect at 0x0 writeback + mov r1, #0x300 @ + orr r3, r3, r1, lsl #20 @ // <<20=0x30000c1e + str r3, [r0, r1, lsl #2] @ // <<2=0xc00 TTB ln + + mov r0, #0x1 @ // + mcr 15, 0, r0, c3, c0, 0 @ //Set Domain perms + mov r0, #0x0 @ // + mcr 15, 0, r0, c7, c7, 0 @ //I&Dcache Invalid + mcr 15, 0, r0, c8, c7, 0 @ //TTB Invalid + mrc 15, 0, r0, c1, c0, 0 @ //Read control reg + orr r0, r0, #0x1000 @ //Icache enable + orr r0, r0, #0x4 @ //Dcache enable + orr r0, r0, #0x1 @ //MMU enable + mcr 15, 0, r0, c1, c0, 0 @ //Make it so + + .size as3525_mmu_init, .-as3525_mmu_init + +#endif /*CONFIG_CPU==AS3525 && !defined(BOOTLOADER) */ #endif /* !IMX31L */