Index: apps/plugins/plugin.lds =================================================================== --- apps/plugins/plugin.lds (revision 20587) +++ apps/plugins/plugin.lds (working copy) @@ -41,11 +41,16 @@ #elif CONFIG_CPU==IMX31L #include "imx31l.h" /* Reserve 1mb for LCD buffer/TTB as in app.lds */ -#define DRAMSIZE (MEMORYSIZE * 0x100000 - 0x100000) - PLUGIN_BUFFER_SIZE - STUBOFFSET - CODEC_SIZE +#define DRAMSIZE (MEMORYSIZE * 0x100000 - 0x100000) - PLUGIN_BUFFER_SIZE - +STUBOFFSET - CODEC_SIZE #elif CONFIG_CPU==AS3525 && MEMORYSIZE <= 2 -#define DRAMSIZE (MEMORYSIZE * 0x100000) - PLUGIN_BUFFER_SIZE - STUBOFFSET +#define TTB_SIZE 0x4000 +#define DRAMSIZE (MEMORYSIZE * 0x100000) - PLUGIN_BUFFER_SIZE - STUBOFFSET \ + - TTB_SIZE #else -#define DRAMSIZE (MEMORYSIZE * 0x100000) - PLUGIN_BUFFER_SIZE - STUBOFFSET - CODEC_SIZE +#define TTB_SIZE 0x4000 +#define DRAMSIZE (MEMORYSIZE * 0x100000) - PLUGIN_BUFFER_SIZE - STUBOFFSET \ + - CODEC_SIZE - TTB_SIZE #endif #if defined(IRIVER_H100_SERIES) || defined(IRIVER_H300) @@ -228,7 +233,7 @@ *(COMMON) . = ALIGN(0x4); } > PLUGIN_RAM - + #if NOCACHE_BASE != 0 .ncbss . + NOCACHE_BASE (NOLOAD) : { Index: firmware/export/as3525.h =================================================================== --- firmware/export/as3525.h (revision 20587) +++ firmware/export/as3525.h (working copy) @@ -26,7 +26,11 @@ #define ECCSIZE 512 #define ECCBYTES 3 +/* AS352X MMU Page Table Entries */ +#define TTB_SIZE 0x4000 /* Mimics OF */ +#define TTB_BASE_ADDR (0x30000000 + MEM*0x100000 - TTB_SIZE) + /* AS352X device base addresses */ Index: firmware/SOURCES =================================================================== --- firmware/SOURCES (revision 20587) +++ firmware/SOURCES (working copy) @@ -266,9 +266,9 @@ drivers/isp1583.c #endif #else /* !defined(HAVE_USBSTACK) */ -#if CONFIG_USBOTG == USBOTG_ISP1362 +#if CONFIG_USBOTG == USBOTG_ISP1362 drivers/isp1362.c -#elif CONFIG_USBOTG == USBOTG_M5636 +#elif CONFIG_USBOTG == USBOTG_M5636 drivers/m5636.c #endif #endif /* !defined(HAVE_USBSTACK) */ @@ -341,7 +341,7 @@ target/arm/i2c-pp.c #elif CONFIG_I2C == I2C_PNX0101 target/arm/pnx0101/i2c-pnx0101.c -#elif CONFIG_I2C == I2C_TCC780X || CONFIG_I2C == I2C_TCC77X +#elif CONFIG_I2C == I2C_TCC780X || CONFIG_I2C == I2C_TCC77X target/arm/i2c-telechips.c #elif CONFIG_I2C == I2C_S3C2440 /* no i2c driver yet */ @@ -457,7 +457,7 @@ target/sh/archos/ata-archos.c target/sh/archos/ata-as-archos.S target/sh/archos/lcd-archos-bitmap.c -target/sh/archos/lcd-as-archos-bitmap.S +target/sh/archos/lcd-as-archos-bitmap.S target/sh/archos/recorder/button-recorder.c target/sh/archos/recorder/power-recorder.c target/sh/archos/recorder/powermgmt-recorder.c @@ -1024,7 +1024,7 @@ target/arm/pnx0101/iriver-ifp7xx/lcd-ifp7xx.c target/arm/pnx0101/iriver-ifp7xx/power-ifp7xx.c target/arm/pnx0101/iriver-ifp7xx/powermgmt-ifp7xx.c -target/arm/pnx0101/iriver-ifp7xx/usb-ifp7xx.c +target/arm/pnx0101/iriver-ifp7xx/usb-ifp7xx.c #ifndef BOOTLOADER target/arm/pnx0101/pcm-pnx0101.c #endif /* BOOTLOADER */ @@ -1094,6 +1094,7 @@ #ifdef SANSA_CLIP #ifndef SIMULATOR +target/arm/mmu-arm.S target/arm/as3525/sansa-clip/lcd-ssd1303.c target/arm/as3525/sansa-clip/lcd-as-clip.S target/arm/as3525/sansa-clip/button-clip.c @@ -1107,6 +1108,7 @@ #ifdef SANSA_E200V2 #ifndef SIMULATOR +target/arm/mmu-arm.S target/arm/as3525/sansa-e200v2/lcd-e200v2.c target/arm/as3525/sansa-e200v2/button-e200v2.c target/arm/as3525/backlight-e200v2-fuze.c @@ -1119,6 +1121,7 @@ #ifdef SANSA_C200V2 #ifndef SIMULATOR +target/arm/mmu-arm.S target/arm/as3525/sansa-c200v2/lcd-c200v2.c target/arm/as3525/sansa-c200v2/button-c200v2.c target/arm/as3525/sansa-c200v2/backlight-c200v2.c @@ -1140,6 +1143,7 @@ #ifdef SANSA_FUZE #ifndef SIMULATOR +target/arm/mmu-arm.S target/arm/as3525/sansa-fuze/button-fuze.c target/arm/as3525/sansa-fuze/lcd-fuze.c target/arm/as3525/backlight-e200v2-fuze.c Index: firmware/target/arm/mmu-arm.h =================================================================== --- firmware/target/arm/mmu-arm.h (revision 20587) +++ firmware/target/arm/mmu-arm.h (working copy) @@ -53,6 +53,12 @@ /* will do writeback */ void invalidate_idcache(void); +/* Set bus speed relationships */ +void mmu_bus_fast(void); +void mmu_bus_sync(void); +void mmu_bus_async(void); + + #define HAVE_CPUCACHE_INVALIDATE #define HAVE_CPUCACHE_FLUSH Index: firmware/target/arm/crt0.S =================================================================== --- firmware/target/arm/crt0.S (revision 20587) +++ firmware/target/arm/crt0.S (working copy) @@ -89,6 +89,36 @@ bhi 1b #endif + /* Setup the MMU, start by disabling */ + + mrc p15, 0, r0, c1, c0, 0 + bic r0, r0, #0x41 /* disable mmu and dcache */ + bic r0, r0, #0x1000 /* disable icache */ + mcr p15, 0, r0, c1, c0, 0 + + bl ttb_init + /* Mimic OF Caching Scheme */ + ldr r0, =0x0 + ldr r1, =0x0 + ldr r2, =0x1000 + mov r3, #0 + bl map_section + + ldr r0, =0x0 + mov r1, r0 @ Flat Mapped + mov r2, #1 + mov r3, #0xc @ writeback cache + bl map_section + + ldr r0, =0x30000000 + mov r1, r0 @ Flat Mapped + mov r2, #1 + mov r3, #0xc @ writeback cache + bl map_section + + bl enable_mmu + bl mmu_bus_async + /* Initialise bss section to zero */ ldr r2, =_edata ldr r3, =_end @@ -97,7 +127,7 @@ cmp r3, r2 strhi r4, [r2], #4 bhi 1b - + /* Set up some stack and munge it with 0xdeadbeef */ ldr sp, =stackend ldr r2, =stackbegin @@ -106,12 +136,12 @@ cmp sp, r2 strhi r3, [r2], #4 bhi 1b - - /* Set up stack for IRQ mode */ + + /* Set up stack for IRQ mode */ msr cpsr_c, #0xd2 ldr sp, =irq_stack - /* Set up stack for FIQ mode */ + /* Set up stack for FIQ mode */ msr cpsr_c, #0xd1 ldr sp, =fiq_stack @@ -148,7 +178,7 @@ b UIE data_abort_handler: - sub r0, lr, #8 + sub r0, lr, #8 mov r1, #2 b UIE Index: firmware/target/arm/as3525/boot.lds =================================================================== --- firmware/target/arm/as3525/boot.lds (revision 20587) +++ firmware/target/arm/as3525/boot.lds (working copy) @@ -5,7 +5,7 @@ OUTPUT_ARCH(arm) STARTUP(target/arm/crt0.o) -#define DRAMSIZE (MEMORYSIZE * 0x100000) +#define DRAMSIZE (MEMORYSIZE * 0x100000) - TTB_SIZE #define DRAMORIG 0x30000000 #define IRAMORIG 0 #define IRAMSIZE 0x50000 Index: firmware/target/arm/as3525/app.lds =================================================================== --- firmware/target/arm/as3525/app.lds (revision 20587) +++ firmware/target/arm/as3525/app.lds (working copy) @@ -25,10 +25,11 @@ #define IRAMSIZE 0x50000 #ifdef LOWMEM -#define DRAMSIZE (MEMORYSIZE * 0x100000) - STUBOFFSET - PLUGINSIZE +#define DRAMSIZE (MEMORYSIZE * 0x100000) - STUBOFFSET - PLUGINSIZE - TTB_SIZE #define CODECORIG (IRAMORIG + IRAMSIZE - CODEC_SIZE) #else -#define DRAMSIZE (MEMORYSIZE * 0x100000) - STUBOFFSET - PLUGINSIZE - CODECSIZE +#define DRAMSIZE (MEMORYSIZE * 0x100000) - STUBOFFSET - PLUGINSIZE - CODECSIZE \ + - TTB_SIZE #define CODECORIG (ENDAUDIOADDR) #endif Index: firmware/target/arm/as3525/ata_sd_as3525.c =================================================================== --- firmware/target/arm/as3525/ata_sd_as3525.c (revision 20587) +++ firmware/target/arm/as3525/ata_sd_as3525.c (working copy) @@ -41,6 +41,7 @@ #include "stdbool.h" #include "ata_idle_notify.h" #include "sd.h" +#include "mmu-arm.h" #ifdef HAVE_HOTSWAP #include "disk.h" @@ -351,7 +352,7 @@ mci_set_clock_divider(drive, 1); /* full speed */ /* - * enable bank switching + * enable bank switching * without issuing this command, we only have access to 1/4 of the blocks * of the first bank (0x1E9E00 blocks, which is the size reported in the * CSD register) @@ -704,6 +705,8 @@ dma_retain(); + invalidate_dcache_range(buf, (count * SECTOR_SIZE)); + while(count) { /* Interrupt handler might set this to true during transfer */ Index: firmware/target/arm/mmu-arm.S =================================================================== --- firmware/target/arm/mmu-arm.S (revision 20587) +++ firmware/target/arm/mmu-arm.S (working copy) @@ -80,7 +80,7 @@ dump_dcache_range: add r1, r0, r1 @ size -> end cmp r1, r0 @ end <= start? - bxls lr @ + bxls lr @ tst r0, #31 @ Check first line for bits set bicne r0, r0, #31 @ Clear low five bits (down) mcrne p15, 0, r0, c7, c14, 1 @ Clean and invalidate line by MVA @@ -132,7 +132,7 @@ mcr p15, 0, r0, c7, c10, 4 @ Data synchronization barrier bx lr @ .size invalidate_dcache, .-invalidate_dcache - + /* * Invalidate entire ICache and DCache * will do writeback @@ -190,18 +190,18 @@ @ 10: superuser - r/w, user - no access @ 4: should be "1" @ 3,2: Cache flags (flags (r3)) - @ 1: Section signature + @ 1: Section signature orr r0, r0, r3 orr r0, r0, #0x410 orr r0, r0, #0x2 - + @ unsigned int* ttbPtr = TTB_BASE + (va >> 20); - @ sections are 1MB size + @ sections are 1MB size mov r1, r1, lsr #20 ldr r3, =TTB_BASE_ADDR - add r1, r3, r1, lsl #0x2 - - @ Add MB to pa, flags are already present in pa, but addition + add r1, r3, r1, lsl #0x2 + + @ Add MB to pa, flags are already present in pa, but addition @ should not effect them @ @ for( ; mb>0; mb--, pa += (1 << 20)) @@ -427,7 +427,7 @@ adds r0, r0, #0x04000000 @ will wrap to zero at loop end bne 1b @ clean_start @ mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer - bx lr @ + bx lr @ .size clean_dcache, .-clean_dcache /* @@ -476,12 +476,65 @@ .type invalidate_idcache, %function .global cpucache_invalidate @ Alias invalidate_idcache: -cpucache_invalidate: +cpucache_invalidate: mov r1, lr @ save lr to r1, call uses r0 only bl invalidate_dcache @ Clean and invalidate entire DCache mcr p15, 0, r0, c7, c5, 0 @ Invalidate ICache (r0=0 from call) mov pc, r1 @ .size invalidate_idcache, .-invalidate_idcache +/* + *void mmu_bus_fast(void) + * + */ + .section .text, "ax", %progbits + .align 2 + .global mmu_bus_fast + .type mmu_bus_fast, %function + +mmu_bus_fast: + mrc 15, 0, r0, c1, c0, 0 @Read control reg + bic r0, r0, #0xc0000000 @Set Fast Bus + mcr 15, 0, r0, c1, c0, 0 @Make it so + bx lr + + .size mmu_bus_fast, .-mmu_bus_fast + +/* + *void mmu_bus_sync(void) + * + */ + .section .text, "ax", %progbits + .align 2 + .global mmu_bus_sync + .type mmu_bus_sync, %function + +mmu_bus_sync: + mrc 15, 0, r0, c1, c0, 0 @Read control reg + bic r0, r0, #0xc0000000 @Clear Bus bits + orr r0, r0, #0x40000000 @Set Sync Bus + mcr 15, 0, r0, c1, c0, 0 @Make it so + bx lr + + .size mmu_bus_sync, .-mmu_bus_sync + +/* + *void mmu_bus_async(void) + * + */ + .section .text, "ax", %progbits + .align 2 + .global mmu_bus_async + .type mmu_bus_async, %function + +mmu_bus_async: + mrc 15, 0, r0, c1, c0, 0 @Read control reg + bic r0, r0, #0xc0000000 @Set Fast Bus + mcr 15, 0, r0, c1, c0, 0 @Make it so + bx lr + + .size mmu_bus_async, .-mmu_bus_async + + #endif /* !IMX31L */