Index: apps/plugins/plugin.lds =================================================================== --- apps/plugins/plugin.lds (revision 20587) +++ apps/plugins/plugin.lds (working copy) @@ -1,4 +1,5 @@ #include "config.h" +#include "cpu.h" /* These output formats should be in the config-files */ @@ -36,16 +37,16 @@ #endif #if CONFIG_CPU==DM320 || CONFIG_CPU==S3C2440 -#include "cpu.h" #define DRAMSIZE (MEMORYSIZE * 0x100000) - STUBOFFSET - PLUGIN_BUFFER_SIZE - CODEC_SIZE - LCD_BUFFER_SIZE - TTB_SIZE #elif CONFIG_CPU==IMX31L #include "imx31l.h" /* Reserve 1mb for LCD buffer/TTB as in app.lds */ -#define DRAMSIZE (MEMORYSIZE * 0x100000 - 0x100000) - PLUGIN_BUFFER_SIZE - STUBOFFSET - CODEC_SIZE +#define DRAMSIZE (MEMORYSIZE * 0x100000 - 0x100000) - PLUGIN_BUFFER_SIZE - +STUBOFFSET - CODEC_SIZE #elif CONFIG_CPU==AS3525 && MEMORYSIZE <= 2 -#define DRAMSIZE (MEMORYSIZE * 0x100000) - PLUGIN_BUFFER_SIZE - STUBOFFSET +#define DRAMSIZE (MEMORYSIZE * 0x100000) - PLUGIN_BUFFER_SIZE - STUBOFFSET - TTB_SIZE #else -#define DRAMSIZE (MEMORYSIZE * 0x100000) - PLUGIN_BUFFER_SIZE - STUBOFFSET - CODEC_SIZE +#define DRAMSIZE (MEMORYSIZE * 0x100000) - PLUGIN_BUFFER_SIZE - STUBOFFSET - CODEC_SIZE - TTB_SIZE #endif #if defined(IRIVER_H100_SERIES) || defined(IRIVER_H300) Index: firmware/export/as3525.h =================================================================== --- firmware/export/as3525.h (revision 20587) +++ firmware/export/as3525.h (working copy) @@ -26,7 +26,11 @@ #define ECCSIZE 512 #define ECCBYTES 3 +/* AS352X MMU Page Table Entries */ +#define TTB_SIZE 0x4000 /* Mimics OF */ +#define TTB_BASE_ADDR (0x30000000 + MEM*0x100000 - TTB_SIZE) + /* AS352X device base addresses */ Index: firmware/SOURCES =================================================================== --- firmware/SOURCES (revision 20587) +++ firmware/SOURCES (working copy) @@ -360,6 +360,7 @@ target/arm/as3525/usb-as3525.c target/arm/as3525/dma-pl081.c target/arm/as3525/ascodec-as3525.c +target/arm/mmu-arm.S #ifndef BOOTLOADER drivers/generic_i2c.c target/arm/adc-as3514.c Index: firmware/target/arm/mmu-arm.h =================================================================== --- firmware/target/arm/mmu-arm.h (revision 20587) +++ firmware/target/arm/mmu-arm.h (working copy) @@ -53,6 +53,12 @@ /* will do writeback */ void invalidate_idcache(void); +/* Set bus speed relationships */ +void mmu_bus_fast(void); +void mmu_bus_sync(void); +void mmu_bus_async(void); + + #define HAVE_CPUCACHE_INVALIDATE #define HAVE_CPUCACHE_FLUSH Index: firmware/target/arm/crt0.S =================================================================== --- firmware/target/arm/crt0.S (revision 20587) +++ firmware/target/arm/crt0.S (working copy) @@ -89,6 +89,36 @@ bhi 1b #endif + /* Setup the MMU, start by disabling */ + + mrc p15, 0, r0, c1, c0, 0 + bic r0, r0, #0x41 /* disable mmu and dcache */ + bic r0, r0, #0x1000 /* disable icache */ + mcr p15, 0, r0, c1, c0, 0 + + bl ttb_init + /* Mimic OF Caching Scheme */ + ldr r0, =0x0 + ldr r1, =0x0 + ldr r2, =0x1000 + mov r3, #0 + bl map_section + + ldr r0, =0x0 + mov r1, r0 @ Flat Mapped + mov r2, #1 + mov r3, #0xc @ writeback cache + bl map_section + + ldr r0, =0x30000000 + mov r1, r0 @ Flat Mapped + mov r2, #1 + mov r3, #0xc @ writeback cache + bl map_section + + bl enable_mmu + bl mmu_bus_async + /* Initialise bss section to zero */ ldr r2, =_edata ldr r3, =_end Index: firmware/target/arm/as3525/boot.lds =================================================================== --- firmware/target/arm/as3525/boot.lds (revision 20587) +++ firmware/target/arm/as3525/boot.lds (working copy) @@ -1,11 +1,12 @@ #include "config.h" +#include "cpu.h" ENTRY(start) OUTPUT_FORMAT(elf32-littlearm) OUTPUT_ARCH(arm) STARTUP(target/arm/crt0.o) -#define DRAMSIZE (MEMORYSIZE * 0x100000) +#define DRAMSIZE (MEMORYSIZE * 0x100000) - TTB_SIZE #define DRAMORIG 0x30000000 #define IRAMORIG 0 #define IRAMSIZE 0x50000 Index: firmware/target/arm/as3525/debug-as3525.c =================================================================== --- firmware/target/arm/as3525/debug-as3525.c (revision 20587) +++ firmware/target/arm/as3525/debug-as3525.c (working copy) @@ -46,19 +46,146 @@ short button_dbop_data(void); #endif -static unsigned read_cp15 (void) +static unsigned read_cp15 (int reg) { unsigned value; - asm volatile ( - "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n":"=r" - (value)::"memory" - ); - return (value); + switch (reg) { + + case 0: /* Register 0 Op2 =0 ID Code */ + asm volatile ( + "mrc p15, 0, %0, c0, c0, 0 @ read control reg\n":"=r" + (value)::"memory" + ); + return (value); + + case 1: /* Register 1 Control */ + asm volatile ( + "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n":"=r" + (value)::"memory" + ); + return (value); + + case 2: /* Register 2 Translation Table Base */ + asm volatile ( + "mrc p15, 0, %0, c2, c0, 0 @ read control reg\n":"=r" + (value)::"memory" + ); + return (value); + + case 3: /* Register 3 Domain Access Control */ + asm volatile ( + "mrc p15, 0, %0, c3, c0, 0 @ read control reg\n":"=r" + (value)::"memory" + ); + return (value); + + case 4: /*Reg 5 Fault Status of prefetch*/ + asm volatile ( + "mrc p15, 0, %0, c5, c0, 1 @ read control reg\n":"=r" + (value)::"memory" + ); + return (value); + + case 5: /* Register 5 Fault Status */ + asm volatile ( + "mrc p15, 0, %0, c5, c0, 0 @ read control reg\n":"=r" + (value)::"memory" + ); + return (value); + + case 6: /* Register 6 Fault address */ + asm volatile ( + "mrc p15, 0, %0, c6, c0, 0 @ read control reg\n":"=r" + (value)::"memory" + ); + return (value); + + case 7: /* Register 0 Op2 =1 Cache type */ + asm volatile ( + "mrc p15, 0, %0, c0, c0, 1 @ read control reg\n":"=r" + (value)::"memory" + ); + return (value); + + case 8: /*Reg 9 Cache lockdown Op2 1=Icache*/ + asm volatile ( + "mrc p15, 0, %0, c9, c0, 1 @ read control reg\n":"=r" + (value)::"memory" + ); + return (value); + + case 9: /*Reg 9 Cache lockdown Op2 0 = Dcache*/ + asm volatile ( + "mrc p15, 0, %0, c9, c0, 0 @ read control reg\n":"=r" + (value)::"memory" + ); + return (value); + + case 10: /*Reg 10 TLB lockdown Op2 0 = Dcache*/ + asm volatile ( + "mrc p15, 0, %0, c10, c0, 0 @ read control reg\n":"=r" + (value)::"memory" + ); + return (value); + + case 11: /*Reg 10 TLB lockdown Op2 1=Icache*/ + asm volatile ( + "mrc p15, 0, %0, c10, c0, 1 @ read control reg\n":"=r" + (value)::"memory" + ); + return (value); + + case 13: /* Register 13 FCSE PID */ + asm volatile ( + "mrc p15, 0, %0, c13, c0, 0 @ read control reg\n":"=r" + (value)::"memory" + ); + return (value); + + case 15: /* Register 15 Test configuration */ + asm volatile ( + "mrc p15, 0, %0, c15, c0, 0 @ read control reg\n":"=r" + (value)::"memory" + ); + return (value); + return (0xdeadbeef); + } + return (0xdeadbeef); } bool __dbg_hw_info(void) { + char buf[50]; + int line; + + lcd_clear_display(); + lcd_setfont(FONT_SYSFIXED); + + while(1) + { + line = 0; + _DEBUG_PRINTF("[CP15 Registers:]"); + _DEBUG_PRINTF("c00 : 0x%8x ID", read_cp15(0)); + _DEBUG_PRINTF("c01 : 0x%8x CacheType", read_cp15(7)); + _DEBUG_PRINTF("c1 : 0x%8x Control", read_cp15(1)); + _DEBUG_PRINTF("c2 : 0x%8x TTB", read_cp15(2)); + _DEBUG_PRINTF("c3 : 0x%8x DomainCTL", read_cp15(3)); + _DEBUG_PRINTF("c50 : 0x%2x Data FSR", read_cp15(5)); + _DEBUG_PRINTF("c51 : 0x%2x Prefetch FSR", read_cp15(4)); + _DEBUG_PRINTF("c6 : 0x%8x FltAddress", read_cp15(6)); + _DEBUG_PRINTF("c90 : 0x%8x DcacheLock", read_cp15(9)); + _DEBUG_PRINTF("c91 : 0x%8x IcacheLock", read_cp15(8)); + _DEBUG_PRINTF("c100: 0x%8x TLBLockD", read_cp15(10)); + _DEBUG_PRINTF("c101: 0x%8x TLBLockI", read_cp15(11)); + _DEBUG_PRINTF("c13 : 0x%8x FCFE PID", read_cp15(13)); + _DEBUG_PRINTF("c15 : 0x%8x Test", read_cp15(15)); + + lcd_update(); + if (button_get_w_tmo(HZ/10) == (DEBUG_CANCEL|BUTTON_REL)) + break; + } + lcd_setfont(FONT_UI); return false; } @@ -84,8 +211,6 @@ _DEBUG_PRINTF("DBOP_DIN: %4x", button_dbop_data()); #endif line++; - _DEBUG_PRINTF("[CP15]"); - _DEBUG_PRINTF("CP15: 0x%8x", read_cp15()); lcd_update(); if (button_get_w_tmo(HZ/10) == (DEBUG_CANCEL|BUTTON_REL)) break; Index: firmware/target/arm/as3525/app.lds =================================================================== --- firmware/target/arm/as3525/app.lds (revision 20587) +++ firmware/target/arm/as3525/app.lds (working copy) @@ -1,4 +1,5 @@ #include "config.h" +#include "cpu.h" ENTRY(start) @@ -20,15 +21,14 @@ #define STUBOFFSET 0 #endif -#include "cpu.h" - #define IRAMSIZE 0x50000 #ifdef LOWMEM -#define DRAMSIZE (MEMORYSIZE * 0x100000) - STUBOFFSET - PLUGINSIZE +#define DRAMSIZE (MEMORYSIZE * 0x100000) - STUBOFFSET - PLUGINSIZE - TTB_SIZE #define CODECORIG (IRAMORIG + IRAMSIZE - CODEC_SIZE) #else -#define DRAMSIZE (MEMORYSIZE * 0x100000) - STUBOFFSET - PLUGINSIZE - CODECSIZE +#define DRAMSIZE (MEMORYSIZE * 0x100000) - STUBOFFSET - PLUGINSIZE - CODECSIZE \ + - TTB_SIZE #define CODECORIG (ENDAUDIOADDR) #endif Index: firmware/target/arm/as3525/ata_sd_as3525.c =================================================================== --- firmware/target/arm/as3525/ata_sd_as3525.c (revision 20587) +++ firmware/target/arm/as3525/ata_sd_as3525.c (working copy) @@ -41,6 +41,7 @@ #include "stdbool.h" #include "ata_idle_notify.h" #include "sd.h" +#include "mmu-arm.h" #ifdef HAVE_HOTSWAP #include "disk.h" @@ -704,6 +705,8 @@ dma_retain(); + invalidate_dcache_range(buf, (count * SECTOR_SIZE)); + while(count) { /* Interrupt handler might set this to true during transfer */ Index: firmware/target/arm/mmu-arm.S =================================================================== --- firmware/target/arm/mmu-arm.S (revision 20587) +++ firmware/target/arm/mmu-arm.S (working copy) @@ -476,12 +476,65 @@ .type invalidate_idcache, %function .global cpucache_invalidate @ Alias invalidate_idcache: -cpucache_invalidate: +cpucache_invalidate: mov r1, lr @ save lr to r1, call uses r0 only bl invalidate_dcache @ Clean and invalidate entire DCache mcr p15, 0, r0, c7, c5, 0 @ Invalidate ICache (r0=0 from call) mov pc, r1 @ .size invalidate_idcache, .-invalidate_idcache +/* + *void mmu_bus_fast(void) + * + */ + .section .text, "ax", %progbits + .align 2 + .global mmu_bus_fast + .type mmu_bus_fast, %function + +mmu_bus_fast: + mrc 15, 0, r0, c1, c0, 0 @Read control reg + bic r0, r0, #0xc0000000 @Set Fast Bus + mcr 15, 0, r0, c1, c0, 0 @Make it so + bx lr + + .size mmu_bus_fast, .-mmu_bus_fast + +/* + *void mmu_bus_sync(void) + * + */ + .section .text, "ax", %progbits + .align 2 + .global mmu_bus_sync + .type mmu_bus_sync, %function + +mmu_bus_sync: + mrc 15, 0, r0, c1, c0, 0 @Read control reg + bic r0, r0, #0xc0000000 @Clear Bus bits + orr r0, r0, #0x40000000 @Set Sync Bus + mcr 15, 0, r0, c1, c0, 0 @Make it so + bx lr + + .size mmu_bus_sync, .-mmu_bus_sync + +/* + *void mmu_bus_async(void) + * + */ + .section .text, "ax", %progbits + .align 2 + .global mmu_bus_async + .type mmu_bus_async, %function + +mmu_bus_async: + mrc 15, 0, r0, c1, c0, 0 @Read control reg + bic r0, r0, #0xc0000000 @Set Fast Bus + mcr 15, 0, r0, c1, c0, 0 @Make it so + bx lr + + .size mmu_bus_async, .-mmu_bus_async + + #endif /* !IMX31L */