Index: apps/plugins/plugin.lds =================================================================== --- apps/plugins/plugin.lds (revision 20720) +++ apps/plugins/plugin.lds (working copy) @@ -1,4 +1,5 @@ #include "config.h" +#include "cpu.h" /* These output formats should be in the config-files */ @@ -43,15 +44,16 @@ #elif CONFIG_CPU==S3C2440 #define LCD_BUFFER_SIZE (LCD_WIDTH*LCD_HEIGHT*2) /* must be 16Kb (0x4000) aligned */ -#define TTB_SIZE (0x4000) +#define TTB_SIZE (0x4000) #define DRAMSIZE (MEMORYSIZE * 0x100000) - STUBOFFSET - PLUGIN_BUFFER_SIZE - CODEC_SIZE - LCD_BUFFER_SIZE - TTB_SIZE -#elif CONFIG_CPU==AS3525 && MEMORYSIZE <= 2 -#define DRAMSIZE (MEMORYSIZE * 0x100000) - PLUGIN_BUFFER_SIZE - STUBOFFSET - +#elif CONFIG_CPU==AS3525 +#if MEMORYSIZE <= 2 +#define DRAMSIZE (MEMORYSIZE * 0x100000) - PLUGIN_BUFFER_SIZE - STUBOFFSET - TTB_SIZE #else -#define DRAMSIZE (MEMORYSIZE * 0x100000) - PLUGIN_BUFFER_SIZE - STUBOFFSET - CODEC_SIZE +#define DRAMSIZE (MEMORYSIZE * 0x100000) - PLUGIN_BUFFER_SIZE - STUBOFFSET - CODEC_SIZE -TTB_SIZE #endif +#endif #if defined(IRIVER_H100_SERIES) || defined(IRIVER_H300) #define ARCH_IRIVER @@ -61,39 +63,47 @@ #define DRAMORIG 0x31000000 #define IRAMORIG 0x1000c000 #define IRAMSIZE 0xc000 + #elif defined(IAUDIO_X5) || defined(IAUDIO_M5) #define DRAMORIG 0x31000000 #define IRAMORIG 0x10010000 #define IRAMSIZE 0x10000 + #elif CONFIG_CPU == PP5022 || CONFIG_CPU == PP5024 /* PP5022/24 have 128KB of IRAM */ #define DRAMORIG 0x00000000 #define IRAMORIG 0x4000c000 #define IRAMSIZE 0x14000 + #elif defined(CPU_PP) /* all other PP's have 96KB of IRAM */ #define DRAMORIG 0x00000000 #define IRAMORIG 0x4000c000 #define IRAMSIZE 0x0c000 + #elif CONFIG_CPU == PNX0101 #define DRAMORIG 0xc00000 + STUBOFFSET #define IRAMORIG 0x407000 #define IRAMSIZE 0x9000 + #elif CONFIG_CPU == IMX31L || CONFIG_CPU == S3C2440 #define DRAMORIG 0x0 + STUBOFFSET #define IRAM DRAM #define IRAMSIZE 0 + #elif CONFIG_CPU==DM320 #define DRAMORIG 0x00900000 + STUBOFFSET #define IRAM DRAM /* The bit of IRAM that is available is used in the core */ #define IRAMSIZE 0 + #elif defined(CPU_TCC780X) || defined(CPU_TCC77X) #define DRAMORIG 0x20000000 /*#define IRAMORIG 0x1000c000 #define IRAMSIZE 0xc000*/ #define IRAM DRAM #define IRAMSIZE 0 + #elif CONFIG_CPU==AS3525 #if MEMORYSIZE <= 2 #define IRAMSIZE 0 /* simulates no IRAM since codec is already entirely in IRAM */ @@ -230,7 +240,7 @@ *(COMMON) . = ALIGN(0x4); } > PLUGIN_RAM - + #if NOCACHE_BASE != 0 .ncbss . + NOCACHE_BASE (NOLOAD) : { Index: firmware/export/as3525.h =================================================================== --- firmware/export/as3525.h (revision 20720) +++ firmware/export/as3525.h (working copy) @@ -26,6 +26,9 @@ #define ECCSIZE 512 #define ECCBYTES 3 +/* AS352X MMU Page Table Entries */ +#define TTB_SIZE 0x4000 /* Mimics OF */ +#define TTB_BASE_ADDR (0x30000000 + MEM*0x100000 - TTB_SIZE) /* AS352X device base addresses */ Index: firmware/SOURCES =================================================================== --- firmware/SOURCES (revision 20720) +++ firmware/SOURCES (working copy) @@ -360,6 +360,7 @@ target/arm/as3525/usb-as3525.c target/arm/as3525/dma-pl081.c target/arm/as3525/ascodec-as3525.c +target/arm/mmu-arm.S #ifndef BOOTLOADER drivers/generic_i2c.c target/arm/adc-as3514.c Index: firmware/target/arm/mmu-arm.h =================================================================== --- firmware/target/arm/mmu-arm.h (revision 20720) +++ firmware/target/arm/mmu-arm.h (working copy) @@ -53,6 +53,14 @@ /* will do writeback */ void invalidate_idcache(void); +/* Enable ICache without MMU */ +void mmu_icache_only(void); + +/* Set bus speed relationships */ +void mmu_bus_fast(void); +void mmu_bus_sync(void); +void mmu_bus_async(void); + #define HAVE_CPUCACHE_INVALIDATE #define HAVE_CPUCACHE_FLUSH Index: firmware/target/arm/crt0.S =================================================================== --- firmware/target/arm/crt0.S (revision 20720) +++ firmware/target/arm/crt0.S (working copy) @@ -87,8 +87,46 @@ ldrhi r5, [r2], #4 strhi r5, [r3], #4 bhi 1b -#endif + /* Setup the MMU, start by disabling */ + + mrc p15, 0, r0, c1, c0, 0 @read control reg + bic r0, r0, #1 @disable mmu + bic r0, r0, #1<<2 @disable dcache + bic r0, r0, #1<<12 @disable icache + mcr p15, 0, r0, c1, c0, 0 @make it so + + /* Set up page table. Access perm bits set to 10(su r/w, user NA) */ + bl ttb_init + + /* + * void map_section(unsigned int pa, unsigned int va, int mb, int flags); + */ + + /* map all memory locations to themselves */ + ldr r0, =0x0 @ Start Map location + ldr r1, =0x0 @ Flat Mapped + ldr r2, =0x1000 @ Num MB + mov r3, #0 @ Cache Flags + bl map_section + /* map IRAM */ + ldr r0, =0x0 + mov r1, r0 @ Flat Mapped + mov r2, #1 + mov r3, #0xc @ writeback cache + bl map_section + /* map DRAM */ + ldr r0, =0x30000000 + mov r1, r0 @ Flat Mapped + mov r2, #2 + mov r3, #0xc @ writeback cache + bl map_section + + bl enable_mmu + bl mmu_bus_async + +#endif /* CONFIG_CPU==AS3525 && !defined(BOOTLOADER) */ + /* Initialise bss section to zero */ ldr r2, =_edata ldr r3, =_end @@ -97,7 +135,7 @@ cmp r3, r2 strhi r4, [r2], #4 bhi 1b - + /* Set up some stack and munge it with 0xdeadbeef */ ldr sp, =stackend ldr r2, =stackbegin @@ -106,12 +144,12 @@ cmp sp, r2 strhi r3, [r2], #4 bhi 1b - - /* Set up stack for IRQ mode */ + + /* Set up stack for IRQ mode */ msr cpsr_c, #0xd2 ldr sp, =irq_stack - /* Set up stack for FIQ mode */ + /* Set up stack for FIQ mode */ msr cpsr_c, #0xd1 ldr sp, =fiq_stack @@ -148,7 +186,7 @@ b UIE data_abort_handler: - sub r0, lr, #8 + sub r0, lr, #8 mov r1, #2 b UIE Index: firmware/target/arm/as3525/pcm-as3525.c =================================================================== --- firmware/target/arm/as3525/pcm-as3525.c (revision 20720) +++ firmware/target/arm/as3525/pcm-as3525.c (working copy) @@ -28,6 +28,7 @@ #include "panic.h" #include "as3514.h" #include "audiohw.h" +#include "mmu-arm.h" #define MAX_TRANSFER (4*((1<<11)-1)) /* maximum data we can transfer via DMA * i.e. 32 bits at once (size of I2SO_DATA) @@ -69,6 +70,7 @@ CGU_PERI |= CGU_I2SOUT_APB_CLOCK_ENABLE; CGU_AUDIO |= (1<<11); +// clean_dcache_range(addr, size); dma_enable_channel(1, (void*)addr, (void*)I2SOUT_DATA, DMA_PERI_I2SOUT, DMAC_FLOWCTRL_DMAC_MEM_TO_PERI, true, false, size >> 2, DMA_S1, dma_callback); Index: firmware/target/arm/as3525/system-as3525.c =================================================================== --- firmware/target/arm/as3525/system-as3525.c (revision 20720) +++ firmware/target/arm/as3525/system-as3525.c (working copy) @@ -28,6 +28,7 @@ #include "clock-target.h" #include "fmradio_i2c.h" #include "button-target.h" +#include "mmu-arm.h" #define default_interrupt(name) \ extern __attribute__((weak,alias("UIRQ"))) void name (void) @@ -214,7 +215,7 @@ MPMC_DYNAMIC_CONFIG_0 |= (1<<19); /* buffer enable */ } -#endif +#endif /* BOOTLOADER */ void system_init(void) { @@ -229,11 +230,7 @@ CGU_PROC = 0; /* fclk 24 MHz */ CGU_PERI &= ~0x7f; /* pclk 24 MHz */ - asm volatile( - "mrc p15, 0, r0, c1, c0 \n" - "orr r0, r0, #0xC0000000 \n" /* asynchronous clocking */ - "mcr p15, 0, r0, c1, c0 \n" - : : : "r0" ); + mmu_bus_async(); /* set bus to asynchronous clocking */ CGU_PLLA = AS3525_PLLA_SETTING; while(!(CGU_INTCTRL & (1<<0))); /* wait until PLLA is locked */ @@ -243,19 +240,9 @@ CGU_PERI |= ((CLK_DIV(AS3525_PLLA_FREQ, AS3525_PCLK_FREQ) - 1) << 2) | 1; /* clk_in = PLLA */ - - /* FIXME: dcache will not be active, since the mmu is not running - * See arm922t datasheet */ - asm volatile( - "mov r0, #0 \n" - "mcr p15, 0, r0, c7, c7 \n" /* invalidate icache & dcache */ - "mrc p15, 0, r0, c1, c0 \n" /* control register */ - "orr r0, r0, #0x1000 \n" /* enable icache */ - "orr r0, r0, #4 \n" /* enable dcache */ - "mcr p15, 0, r0, c1, c0 \n" - : : : "r0" ); - #ifdef BOOTLOADER + mmu_icache_only(); /*Enable Icache in bootloader with MMU disabled */ + /* mmu & dcache enabled in crt0.S for main build*/ sdram_init(); #endif /* BOOTLOADER */ @@ -323,4 +310,4 @@ CGU_PROC = (CGU_PROC & 0x0f) | ((divider-1) << 4); } #endif /* HAVE_ADJUSTABLE_CPU_FREQ */ -#endif /* BOOTLOADER */ +#endif /* !BOOTLOADER */ Index: firmware/target/arm/as3525/debug-as3525.c =================================================================== --- firmware/target/arm/as3525/debug-as3525.c (revision 20720) +++ firmware/target/arm/as3525/debug-as3525.c (working copy) @@ -46,19 +46,146 @@ short button_dbop_data(void); #endif -static unsigned read_cp15 (void) +static unsigned read_cp15 (int reg) { unsigned value; - asm volatile ( - "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n":"=r" - (value)::"memory" - ); - return (value); + switch (reg) { + + case 0: /* Register 0 Op2 =0 ID Code */ + asm volatile ( + "mrc p15, 0, %0, c0, c0, 0 @ read control reg\n":"=r" + (value)::"memory" + ); + return (value); + + case 1: /* Register 1 Control */ + asm volatile ( + "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n":"=r" + (value)::"memory" + ); + return (value); + + case 2: /* Register 2 Translation Table Base */ + asm volatile ( + "mrc p15, 0, %0, c2, c0, 0 @ read control reg\n":"=r" + (value)::"memory" + ); + return (value); + + case 3: /* Register 3 Domain Access Control */ + asm volatile ( + "mrc p15, 0, %0, c3, c0, 0 @ read control reg\n":"=r" + (value)::"memory" + ); + return (value); + + case 4: /*Reg 5 Fault Status of prefetch*/ + asm volatile ( + "mrc p15, 0, %0, c5, c0, 1 @ read control reg\n":"=r" + (value)::"memory" + ); + return (value); + + case 5: /* Register 5 Fault Status */ + asm volatile ( + "mrc p15, 0, %0, c5, c0, 0 @ read control reg\n":"=r" + (value)::"memory" + ); + return (value); + + case 6: /* Register 6 Fault address */ + asm volatile ( + "mrc p15, 0, %0, c6, c0, 0 @ read control reg\n":"=r" + (value)::"memory" + ); + return (value); + + case 7: /* Register 0 Op2 =1 Cache type */ + asm volatile ( + "mrc p15, 0, %0, c0, c0, 1 @ read control reg\n":"=r" + (value)::"memory" + ); + return (value); + + case 8: /*Reg 9 Cache lockdown Op2 1=Icache*/ + asm volatile ( + "mrc p15, 0, %0, c9, c0, 1 @ read control reg\n":"=r" + (value)::"memory" + ); + return (value); + + case 9: /*Reg 9 Cache lockdown Op2 0 = Dcache*/ + asm volatile ( + "mrc p15, 0, %0, c9, c0, 0 @ read control reg\n":"=r" + (value)::"memory" + ); + return (value); + + case 10: /*Reg 10 TLB lockdown Op2 0 = Dcache*/ + asm volatile ( + "mrc p15, 0, %0, c10, c0, 0 @ read control reg\n":"=r" + (value)::"memory" + ); + return (value); + + case 11: /*Reg 10 TLB lockdown Op2 1=Icache*/ + asm volatile ( + "mrc p15, 0, %0, c10, c0, 1 @ read control reg\n":"=r" + (value)::"memory" + ); + return (value); + + case 13: /* Register 13 FCSE PID */ + asm volatile ( + "mrc p15, 0, %0, c13, c0, 0 @ read control reg\n":"=r" + (value)::"memory" + ); + return (value); + + case 15: /* Register 15 Test configuration */ + asm volatile ( + "mrc p15, 0, %0, c15, c0, 0 @ read control reg\n":"=r" + (value)::"memory" + ); + return (value); + return (0xdeadbeef); + } + return (0xdeadbeef); } bool __dbg_hw_info(void) { + char buf[50]; + int line; + + lcd_clear_display(); + lcd_setfont(FONT_SYSFIXED); + + while(1) + { + line = 0; + _DEBUG_PRINTF("[CP15 Registers:]"); + _DEBUG_PRINTF("c00 : 0x%8x ID", read_cp15(0)); + _DEBUG_PRINTF("c01 : 0x%8x CacheType", read_cp15(7)); + _DEBUG_PRINTF("c1 : 0x%8x Control", read_cp15(1)); + _DEBUG_PRINTF("c2 : 0x%8x TTB", read_cp15(2)); + _DEBUG_PRINTF("c3 : 0x%8x DomainCTL", read_cp15(3)); + _DEBUG_PRINTF("c50 : 0x%2x Data FSR", read_cp15(5)); + _DEBUG_PRINTF("c51 : 0x%2x Prefetch FSR", read_cp15(4)); + _DEBUG_PRINTF("c6 : 0x%8x FltAddress", read_cp15(6)); + _DEBUG_PRINTF("c90 : 0x%8x DcacheLock", read_cp15(9)); + _DEBUG_PRINTF("c91 : 0x%8x IcacheLock", read_cp15(8)); + _DEBUG_PRINTF("c100: 0x%8x TLBLockD", read_cp15(10)); + _DEBUG_PRINTF("c101: 0x%8x TLBLockI", read_cp15(11)); + _DEBUG_PRINTF("c13 : 0x%8x FCFE PID", read_cp15(13)); + _DEBUG_PRINTF("c15 : 0x%8x Test", read_cp15(15)); + + lcd_update(); + if (button_get_w_tmo(HZ/10) == (DEBUG_CANCEL|BUTTON_REL)) + break; + } + lcd_setfont(FONT_UI); return false; } @@ -84,8 +211,6 @@ _DEBUG_PRINTF("DBOP_DIN: %4x", button_dbop_data()); #endif line++; - _DEBUG_PRINTF("[CP15]"); - _DEBUG_PRINTF("CP15: 0x%8x", read_cp15()); lcd_update(); if (button_get_w_tmo(HZ/10) == (DEBUG_CANCEL|BUTTON_REL)) break; Index: firmware/target/arm/as3525/app.lds =================================================================== --- firmware/target/arm/as3525/app.lds (revision 20720) +++ firmware/target/arm/as3525/app.lds (working copy) @@ -1,4 +1,5 @@ #include "config.h" +#include "cpu.h" ENTRY(start) @@ -20,14 +21,14 @@ #define STUBOFFSET 0 #endif -#include "cpu.h" + #ifdef LOWMEM -#define DRAMSIZE (MEMORYSIZE * 0x100000) - STUBOFFSET - PLUGINSIZE +#define DRAMSIZE (MEMORYSIZE * 0x100000) - STUBOFFSET - PLUGINSIZE -TTB_SIZE #define CODECORIG (IRAMORIG + 0x50000 - CODEC_SIZE) #define IRAMSIZE (0x50000 - CODEC_SIZE) #else -#define DRAMSIZE (MEMORYSIZE * 0x100000) - STUBOFFSET - PLUGINSIZE - CODECSIZE +#define DRAMSIZE (MEMORYSIZE * 0x100000) - STUBOFFSET - PLUGINSIZE - CODECSIZE - TTB_SIZE #define CODECORIG (ENDAUDIOADDR) #define IRAMSIZE (0x20000) #endif Index: firmware/target/arm/as3525/ata_sd_as3525.c =================================================================== --- firmware/target/arm/as3525/ata_sd_as3525.c (revision 20720) +++ firmware/target/arm/as3525/ata_sd_as3525.c (working copy) @@ -41,6 +41,7 @@ #include "stdbool.h" #include "ata_idle_notify.h" #include "sd.h" +#include "mmu-arm.h" #ifdef HAVE_HOTSWAP #include "disk.h" @@ -351,7 +352,7 @@ mci_set_clock_divider(drive, 1); /* full speed */ /* - * enable bank switching + * enable bank switching * without issuing this command, we only have access to 1/4 of the blocks * of the first bank (0x1E9E00 blocks, which is the size reported in the * CSD register) @@ -708,6 +709,8 @@ dma_retain(); +// invalidate_dcache_range(buf, (count * SECTOR_SIZE)); + while(count) { /* 128 * 512 = 2^16, and doesn't fit in the 16 bits of DATA_LENGTH @@ -740,14 +743,20 @@ goto sd_transfer_error; } - if(write) + if(write) /* system mem -> peripheral */ + { + clean_dcache_range(dma_buf, (transfer * SECTOR_SIZE)); dma_enable_channel(0, dma_buf, MCI_FIFO(drive), (drive == INTERNAL_AS3525) ? DMA_PERI_SD : DMA_PERI_SD_SLOT, DMAC_FLOWCTRL_PERI_MEM_TO_PERI, true, false, 0, DMA_S8, NULL); - else + } + else /* peripheral -> system mem */ + { dma_enable_channel(0, MCI_FIFO(drive), dma_buf, (drive == INTERNAL_AS3525) ? DMA_PERI_SD : DMA_PERI_SD_SLOT, DMAC_FLOWCTRL_PERI_PERI_TO_MEM, false, true, 0, DMA_S8, NULL); + dump_dcache_range(dma_buf, (transfer * SECTOR_SIZE)); + } MCI_DATA_TIMER(drive) = 0x1000000; /* FIXME: arbitrary */ MCI_DATA_LENGTH(drive) = transfer * card_info[drive].block_size; @@ -756,8 +765,8 @@ (1<<3) /* DMA */ | (9<<4) /* 2^9 = 512 */ ; + wakeup_wait(&transfer_completion_signal, TIMEOUT_BLOCK); - wakeup_wait(&transfer_completion_signal, TIMEOUT_BLOCK); if(!retry) { if(unaligned_transfer && !write) @@ -767,6 +776,7 @@ count -= transfer; } + last_disk_activity = current_tick; if(!send_cmd(drive, SD_STOP_TRANSMISSION, 0, MCI_NO_FLAGS, NULL)) Index: firmware/target/arm/mmu-arm.S =================================================================== --- firmware/target/arm/mmu-arm.S (revision 20720) +++ firmware/target/arm/mmu-arm.S (working copy) @@ -483,5 +483,80 @@ mov pc, r1 @ .size invalidate_idcache, .-invalidate_idcache + +/* + *void mmu_icache_only(void) + * + */ + .section .text, "ax", %progbits + .align 2 + .global mmu_icache_only + .type mmu_icache_only, %function + +mmu_icache_only: + mov r0, #0 + mcr p15, 0, r0, c7, c7 @ invalidate icache & dcache + mrc p15, 0, r0, c1, c0 @ read control register + orr r0, r0, #1<<12 @ enable icache + bic r0, r0, #1<<2 @ disable dcache + bic r0, r0, #1 @ disable mmu + mcr p15, 0, r0, c1, c0 @ make it so + bx lr + + .size mmu_icache_only, .-mmu_icache_only + +/* + *void mmu_bus_fast(void) + * + */ + .section .text, "ax", %progbits + .align 2 + .global mmu_bus_fast + .type mmu_bus_fast, %function + +mmu_bus_fast: + mrc 15, 0, r0, c1, c0, 0 @Read control reg + bic r0, r0, #0xc0000000 @Set Fast Bus + mcr 15, 0, r0, c1, c0, 0 @Make it so + bx lr + + .size mmu_bus_fast, .-mmu_bus_fast + +/* + *void mmu_bus_sync(void) + * + */ + .section .text, "ax", %progbits + .align 2 + .global mmu_bus_sync + .type mmu_bus_sync, %function + +mmu_bus_sync: + mrc 15, 0, r0, c1, c0, 0 @Read control reg + bic r0, r0, #0xc0000000 @Clear Bus bits + orr r0, r0, #0x40000000 @Set Sync Bus + mcr 15, 0, r0, c1, c0, 0 @Make it so + bx lr + + .size mmu_bus_sync, .-mmu_bus_sync + +/* + *void mmu_bus_async(void) + * + */ + .section .text, "ax", %progbits + .align 2 + .global mmu_bus_async + .type mmu_bus_async, %function + +mmu_bus_async: + mrc 15, 0, r0, c1, c0, 0 @Read control reg + bic r0, r0, #0xc0000000 @Set Fast Bus + mcr 15, 0, r0, c1, c0, 0 @Make it so + bx lr + + .size mmu_bus_async, .-mmu_bus_async + + #endif /* !IMX31L */