Index: firmware/target/arm/crt0.S
===================================================================
--- firmware/target/arm/crt0.S	(revision 20865)
+++ firmware/target/arm/crt0.S	(working copy)
@@ -87,6 +87,61 @@
     ldrhi   r5, [r2], #4
     strhi   r5, [r3], #4
     bhi     1b
+
+#if  USE_MMU  /****************MMU & Mapping module *************************/
+    /* Setup the MMU, start by disabling */
+
+    mrc     p15, 0, r0, c1, c0, 0           @read control reg
+    bic     r0, r0, #1                      @disable mmu
+    bic     r0, r0, #1<<2                   @disable dcache
+    bic     r0, r0, #1<<12                  @disable icache
+    mcr     p15, 0, r0, c1, c0, 0           @make it so
+
+    /*  Set up page table.  Access perm bits set to 10(su r/w, user NA)  */
+    bl      ttb_init
+
+   /*
+    * void map_section(unsigned int pa, unsigned int va, int mb, int flags);
+    */
+    @      CACHE_ALL   0x0C
+    @      CACHE_NONE  0
+    @      BUFFERED    0x04
+
+    /* map all memory locations to themselves uncached */
+    ldr     r0, =0x0                        @ Start Map location
+    ldr     r1, =0x0                        @ Flat Mapped
+    ldr     r2, =0x1000                     @ Num MB
+    mov     r3, #0                          @ Cache Flags
+    bl      map_section
+    /*    map IRAM   */
+    ldr     r0, =0x0                        @ IRAM origin
+    mov     r1, r0                          @ Flat Mapped
+    mov     r2, #1
+    mov     r3, #0xc                        @ writeback cache
+    bl      map_section
+    /*  Mirror IRAM  */
+    ldr     r0, =0x0                        @ IRAM origin
+    ldr     r1, =0x00100000                 @ Mirror IRAM for noncache use
+    mov     r2, #1
+    mov     r3, #0                          @ uncached
+    bl      map_section
+    /*   map DRAM  */
+    ldr     r0, =0x30000000                 @ DRAM origin
+    mov     r1, r0                          @ Flat Mapped
+    mov     r2, #8
+    mov     r3, #0xc                        @ writeback cache
+    bl      map_section
+    /*  Mirror DRAM  */
+    ldr     r0, =0x30000000                 @ DRAM origin
+    ldr     r1, =0x40000000                 @ Mirror DRAM for noncache use
+    mov     r2, #8
+    mov     r3, #0                          @ uncached
+    bl      map_section
+
+    bl      enable_mmu
+
+#endif  /**********************MMU & Mapping module *************************/
+
 #endif
 
     /* Initialise bss section to zero */
Index: firmware/target/arm/as3525/dma-pl081.c
===================================================================
--- firmware/target/arm/as3525/dma-pl081.c	(revision 20865)
+++ firmware/target/arm/as3525/dma-pl081.c	(working copy)
@@ -24,6 +24,7 @@
 #include "pl081.h"
 #include "dma-target.h"
 #include "panic.h"
 
 static int dma_used = 0;
 static void (*dma_callback[2])(void); /* 2 channels */
@@ -70,6 +71,21 @@
 
     DMAC_CH_LLI(channel) = 0;    /* we use contigous memory, so don't use the LLI */
 
+#if USE_MMU
+    /* use mirrored uncached virtual addresses for DMA */
+    if((unsigned long)dst >= 0x30000000 &&
+       (unsigned long)dst < (MEM * 0x100000))         /* SDRAM */
+        dst += 0x10000000;
+    else if((unsigned long)dst < 0x00050000)    /* IRAM */
+        dst += 0x00100000;
+
+    if((unsigned long)src >= 0x30000000 &&
+       (unsigned long)src < (MEM * 0x100000))         /* SDRAM */
+        dst += 0x10000000;
+    else if((unsigned long)src < 0x00050000)    /* IRAM */
+        dst += 0x00100000;
+#endif
+
     /* specify address increment */
     if(src_inc)
         control |= (1<<26);