Index: firmware/target/arm/s5l8700/ipodnano2g/nand-nano2g.c
===================================================================
--- firmware/target/arm/s5l8700/ipodnano2g/nand-nano2g.c	(Revision 24135)
+++ firmware/target/arm/s5l8700/ipodnano2g/nand-nano2g.c	(Arbeitskopie)
@@ -21,6 +21,7 @@
 
 
 #include "config.h"
+#include "panic.h"
 #include "system.h"
 #include "kernel.h"
 #include "cpu.h"
@@ -182,11 +183,13 @@
     return nand_wait_cmddone();
 }
 
+uint32_t nand_wait_status_ready(uint32_t bank);
+
 uint32_t nand_reset(uint32_t bank)
 {
     nand_set_fmctrl0(bank, 0);
     if (nand_send_cmd(NAND_CMD_RESET)) return 1;
-    if (nand_wait_chip_ready(bank)) return 1;
+    /* if (nand_wait_chip_ready(bank)) panicf("nand_reset:nand_wait_chip_ready:%d",bank); */ /* this fails on some players(always seems to be bank 2) */
     FMCTRL1 = FMCTRL1_CLEARRFIFO | FMCTRL1_CLEARWFIFO;
     return 0;
 }
@@ -197,7 +200,7 @@
     nand_set_fmctrl0(bank, 0);
     if ((FMCSTAT & (FMCSTAT_BANK0READY << bank)))
         FMCSTAT = (FMCSTAT_BANK0READY << bank);
-    FMCTRL1 = FMCTRL1_CLEARRFIFO | FMCTRL1_CLEARWFIFO;
+    FMCTRL1 = FMCTRL1_CLEARRFIFO;
     if (nand_send_cmd(NAND_CMD_GET_STATUS)) return 1;
     while (1)
     {
@@ -234,6 +237,7 @@
     if (!direction) invalidate_dcache();
     if (nand_wait_addrdone()) return 1;
     if (!direction) FMCTRL1 = FMCTRL1_CLEARRFIFO | FMCTRL1_CLEARWFIFO;
+    else FMCTRL1 = FMCTRL1_CLEARRFIFO;
     return 0;
 }
 
@@ -288,17 +292,18 @@
 {
     mutex_lock(&nand_mtx);
     uint32_t result;
-    if (nand_reset(bank)) return nand_unlock(0xFFFFFFFF);
+    nand_set_fmctrl0(bank, 0); /* select bank */
     if (nand_send_cmd(0x90)) return nand_unlock(0xFFFFFFFF);
     FMANUM = 0;
     FMADDR0 = 0;
     FMCTRL1 = FMCTRL1_DOTRANSADDR;
     if (nand_wait_cmddone()) return nand_unlock(0xFFFFFFFF);
+    nand_set_fmctrl0(bank, 0);
     FMDNUM = 4;
     FMCTRL1 = FMCTRL1_DOREADDATA;
     if (nand_wait_addrdone()) return nand_unlock(0xFFFFFFFF);
     result = FMFIFO;
-    FMCTRL1 = FMCTRL1_CLEARRFIFO | FMCTRL1_CLEARWFIFO;
+    FMCTRL1 = FMCTRL1_CLEARRFIFO;
     return nand_unlock(result);
 }
 
@@ -314,7 +319,7 @@
 
 void nand_power_up(void)
 {
-    uint32_t i;
+    int i;
     mutex_lock(&nand_mtx);
     nand_last_activity_value = current_tick;
     PWRCONEXT &= ~0x40;
@@ -327,11 +332,12 @@
     PDAT4 = 0;
     PCON5 = (PCON5 & ~0xF) | 3;
     PUNK5 = 1;
-    pmu_ldo_set_voltage(4, 0x15);
     pmu_ldo_power_on(4);
     sleep(HZ / 20);
     nand_last_activity_value = current_tick;
-    for (i = 0; i < 4; i++) nand_reset(i);
+    for (i = 0; i < 4; i++) if(nand_reset(i)) panicf("nand_power_up:nand_reset:%d",i);
+    /* we can call nand_wait_status_ready here with bank = 0. according to the datasheet waiting for status ready is not bank dependant(nand_wait_status_ready does just a little bit more) */
+    if(nand_wait_status_ready(0)) panicf("nand_power_up_nand_wait_stauts_ready");
     nand_powered = 1;
     nand_last_activity_value = current_tick;
     mutex_unlock(&nand_mtx);
@@ -525,7 +531,7 @@
         nand_tunk2[i] = nand_deviceinfotable[nand_type[i]].tunk2;
         nand_tunk3[i] = nand_deviceinfotable[nand_type[i]].tunk3;
     }
-    if (nand_type[0] == 0xFFFFFFFF) return 1;
+    if (nand_type[0] == 0xFFFFFFFF) panicf("nand_device_init");
 
     nand_last_activity_value = current_tick;
     create_thread(nand_thread, nand_stack,