Index: firmware/target/arm/as3525/system-as3525.c =================================================================== --- firmware/target/arm/as3525/system-as3525.c (revision 28616) +++ firmware/target/arm/as3525/system-as3525.c (working copy) @@ -33,6 +33,9 @@ #include "backlight-target.h" #include "lcd.h" +#define I2C2_CPSR0 *((volatile unsigned int *)(I2C_AUDIO_BASE + 0x1C)) +#define I2C2_CPSR1 *((volatile unsigned int *)(I2C_AUDIO_BASE + 0x20)) + #define default_interrupt(name) \ extern __attribute__((weak,alias("UIRQ"))) void name (void) @@ -286,7 +289,7 @@ #endif /* Initialize power management settings */ - ascodec_write(AS3514_CVDD_DCDC3, AS314_CP_DCDC3_SETTING); + ascodec_write(AS3514_CVDD_DCDC3, AS314_CP_DCDC3_SETTING|CVDD_1_10); #if CONFIG_TUNER fmradio_i2c_init(); #endif @@ -354,7 +357,7 @@ { if(frequency == CPUFREQ_MAX) { -#ifdef HAVE_ADJUSTABLE_CPU_VOLTAGE +#if defined(HAVE_ADJUSTABLE_CPU_VOLTAGE) && (CPUFREQ_MAX > 200000000) /* Increasing frequency so boost voltage before change */ ascodec_write(AS3514_CVDD_DCDC3, (AS314_CP_DCDC3_SETTING | CVDD_1_20)); @@ -373,11 +376,31 @@ /* synchronous bus clocking had issues on some players */ "mcr p15, 0, r0, c1, c0 \n" : : : "r0" ); - + /* Set DBOP frequency */ + //CGU_DBOP = (1<<3) | (CLK_DIV(62000000, AS3525_DBOP_FREQ) - 1); + /* Set I2C frequency */ + I2C2_CPSR0 = AS3525_I2C_PRESCALER_BOOSTED & 0xFF; /* 8 lsb */ + I2C2_CPSR1 = (AS3525_I2C_PRESCALER_BOOSTED >> 8) & 0x3; /* 2 msb */ + /* Set PCLK frequency */ + CGU_PERI = ((CGU_PERI & ~0x7F) | /* reset divider & clksel bits */ + ((AS3525_PCLK_DIV0_BOOSTED) << 2) | + (AS3525_PCLK_DIV1_BOOSTED << 6) | + AS3525_PCLK_SEL); cpu_frequency = CPUFREQ_MAX; } else { + /* Set DBOP frequency */ + //CGU_DBOP = (1<<3) | (AS3525_DBOP_DIV); + /* Set I2C frequency */ + I2C2_CPSR0 = AS3525_I2C_PRESCALER & 0xFF; /* 8 lsb */ + I2C2_CPSR1 = (AS3525_I2C_PRESCALER >> 8) & 0x3; /* 2 msb */ + /* Set PCLK frequency */ + CGU_PERI = ((CGU_PERI & ~0x7F) | /* reset divider & clksel bits */ + (AS3525_PCLK_DIV0 << 2) | + (AS3525_PCLK_DIV1 << 6) | + AS3525_PCLK_SEL); + asm volatile( "mrc p15, 0, r0, c1, c0 \n" "bic r0, r0, #3<<30 \n" /* fastbus clocking */ @@ -387,7 +410,7 @@ /* FCLK is unused so put it to the lowest freq we can */ CGU_PROC = ((0xf << 4) | (0x3 << 2) | AS3525_CLK_MAIN); -#ifdef HAVE_ADJUSTABLE_CPU_VOLTAGE +#if defined(HAVE_ADJUSTABLE_CPU_VOLTAGE) && (CPUFREQ_MAX > 200000000) /* Decreasing frequency so reduce voltage after change */ ascodec_write(AS3514_CVDD_DCDC3, (AS314_CP_DCDC3_SETTING | CVDD_1_10)); #endif /* HAVE_ADJUSTABLE_CPU_VOLTAGE */ Index: firmware/target/arm/as3525/clock-target.h =================================================================== --- firmware/target/arm/as3525/clock-target.h (revision 28616) +++ firmware/target/arm/as3525/clock-target.h (working copy) @@ -114,17 +114,19 @@ /* *5/8 = 240MHz 120, 80, 60, 48, 40 */ //#define AS3525_PLLA_SETTING 0x2630 -#define AS3525_FCLK_PREDIV 0 /* div = (8-n)/8 Enter manually & postdiv will be calculated*/ +#define AS3525_FCLK_PREDIV 2 /* div = (8-n)/8 Enter manually & postdiv will be calculated*/ /* 0 gives you the PLLA 1st line choices, 1 the 2nd line etc. */ -#define AS3525_FCLK_FREQ 248000000 /* Boosted FCLK frequency */ -#define AS3525_DRAM_FREQ 62000000 /* Initial DRAM frequency */ +#define AS3525_FCLK_FREQ 186000000 /* Boosted FCLK frequency - over 200MHz */ + /* requires CVDDp bumped to 1.2V */ +#define AS3525_DRAM_FREQ 31000000 /* Initial DRAM frequency */ +#define AS3525_DRAM_FREQ_BOOSTED 62000000 /* AS3525_PCLK_FREQ != AS3525_DRAM_FREQ/1 will boot to white lcd screen */ #endif /* CONFIG_CPU == AS3525v2 */ #define AS3525_PCLK_FREQ (AS3525_DRAM_FREQ/1) /* PCLK divided from DRAM freq */ - +#define AS3525_PCLK_FREQ_BOOSTED (AS3525_DRAM_FREQ_BOOSTED/1) #define AS3525_DBOP_FREQ (AS3525_PCLK_FREQ/1) /* DBOP divided from PCLK freq */ /** ****************************************************************************/ @@ -169,6 +171,9 @@ /*unable to use AS3525_PCLK_DIV1 != 0 successfuly so far*/ #define AS3525_PCLK_DIV1 (CLK_DIV(AS3525_DRAM_FREQ, AS3525_PCLK_FREQ) - 1)/* div = 1/(n+1)*/ #define AS3525_PCLK_DIV0 (CLK_DIV(AS3525_PLLA_FREQ, AS3525_DRAM_FREQ) - 1) /*div=1/(n+1)*/ +#define AS3525_PCLK_DIV1_BOOSTED (CLK_DIV(AS3525_DRAM_FREQ_BOOSTED, AS3525_PCLK_FREQ_BOOSTED) - 1) +#define AS3525_PCLK_DIV0_BOOSTED (CLK_DIV(AS3525_PLLA_FREQ, AS3525_PCLK_FREQ_BOOSTED) - 1) + #else #define AS3525_PCLK_SEL AS3525_CLK_FCLK @@ -179,6 +184,7 @@ /* PCLK as Source */ #define AS3525_DBOP_DIV (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1) /*div=1/(n+1)*/ #define AS3525_I2C_PRESCALER CLK_DIV(AS3525_PCLK_FREQ, AS3525_I2C_FREQ) + #define AS3525_I2C_PRESCALER_BOOSTED CLK_DIV(AS3525_PCLK_FREQ_BOOSTED, AS3525_I2C_FREQ) #define AS3525_I2C_FREQ 400000 #define AS3525_SD_IDENT_DIV ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SD_IDENT_FREQ) / 2) - 1) #define AS3525_SD_IDENT_FREQ 400000 /* must be between 100 & 400 kHz */ Index: firmware/target/arm/as3525/sd-as3525.c =================================================================== --- firmware/target/arm/as3525/sd-as3525.c (revision 28616) +++ firmware/target/arm/as3525/sd-as3525.c (working copy) @@ -116,8 +116,8 @@ static tCardInfo card_info[NUM_DRIVES]; /* maximum timeouts recommanded in the SD Specification v2.00 */ -#define SD_MAX_READ_TIMEOUT ((AS3525_PCLK_FREQ) / 1000 * 100) /* 100 ms */ -#define SD_MAX_WRITE_TIMEOUT ((AS3525_PCLK_FREQ) / 1000 * 250) /* 250 ms */ +#define SD_MAX_READ_TIMEOUT ((AS3525_PCLK_FREQ*(cpu_frequency==CPUFREQ_MAX?2:1)) / 1000 * 100) /* 100 ms */ +#define SD_MAX_WRITE_TIMEOUT ((AS3525_PCLK_FREQ*(cpu_frequency==CPUFREQ_MAX?2:1)) / 1000 * 250) /* 250 ms */ /* for compatibility */ static long last_disk_activity = -1; @@ -144,6 +144,7 @@ static unsigned char aligned_buffer[UNALIGNED_NUM_SECTORS* SD_BLOCK_SIZE] __attribute__((aligned(32))); /* align on cache line size */ static unsigned char *uncached_buffer = AS3525_UNCACHED_ADDR(&aligned_buffer[0]); +extern long cpu_frequency; static inline void mci_delay(void) { udelay(1000) ; }