Index: dbop-as3525.c =================================================================== --- dbop-as3525.c (revision 28932) +++ dbop-as3525.c (working copy) @@ -43,7 +43,7 @@ /* make sure that the DBOP FIFO is empty */ while ((DBOP_STAT & (1<<10)) == 0); - int delay = 10; + int delay = 20; while (delay--) asm volatile ("nop\n"); /* write DBOP_DOUT to pre-charge DBOP data lines with a defined level */ Index: system-as3525.c =================================================================== --- system-as3525.c (revision 28932) +++ system-as3525.c (working copy) @@ -33,6 +33,12 @@ #include "backlight-target.h" #include "lcd.h" +/* FIXME */ +#define I2C2_CPSR0 *((volatile unsigned int *)(I2C_AUDIO_BASE + 0x1C)) +#define I2C2_CPSR1 *((volatile unsigned int *)(I2C_AUDIO_BASE + 0x20)) +extern void sd_set_boosted_divider(void); +extern void sd_set_unboosted_divider(void); + #define default_interrupt(name) \ extern __attribute__((weak,alias("UIRQ"))) void name (void) @@ -286,7 +292,12 @@ #endif /* Initialize power management settings */ +#if CONFIG_CPU == AS3525 + ascodec_write(AS3514_CVDD_DCDC3, AS314_CP_DCDC3_SETTING|CVDD_1_10); +#else ascodec_write(AS3514_CVDD_DCDC3, AS314_CP_DCDC3_SETTING); +#endif + #if CONFIG_TUNER fmradio_i2c_init(); #endif @@ -354,7 +365,9 @@ { if(frequency == CPUFREQ_MAX) { -#ifdef HAVE_ADJUSTABLE_CPU_VOLTAGE +#if defined(HAVE_ADJUSTABLE_CPU_VOLTAGE) && (CPUFREQ_MAX > 200000000) + /* This doesn't work anymore. It was written before ascodec + was switched to use interrupts */ /* Increasing frequency so boost voltage before change */ ascodec_write(AS3514_CVDD_DCDC3, (AS314_CP_DCDC3_SETTING | CVDD_1_20)); @@ -374,10 +387,35 @@ "mcr p15, 0, r0, c1, c0 \n" : : : "r0" ); +#ifdef HAVE_MULTIDRIVE + /* Set uSD frequency */ + sd_set_boosted_divider(); +#endif + /* Set I2C frequency */ + I2C2_CPSR0 = AS3525_I2C_PRESCALER_BOOSTED & 0xFF; /* 8 lsb */ + I2C2_CPSR1 = (AS3525_I2C_PRESCALER_BOOSTED >> 8) & 0x3; /* 2 msb */ + /* Set PCLK frequency */ + CGU_PERI = ((CGU_PERI & ~0x7F) | /* reset divider & clksel bits */ + (AS3525_PCLK_DIV0_BOOSTED << 2) | + (AS3525_PCLK_DIV1_BOOSTED << 6) | + AS3525_PCLK_SEL); cpu_frequency = CPUFREQ_MAX; } else { + /* Set I2C frequency */ + I2C2_CPSR0 = AS3525_I2C_PRESCALER & 0xFF; /* 8 lsb */ + I2C2_CPSR1 = (AS3525_I2C_PRESCALER >> 8) & 0x3; /* 2 msb */ + /* Set PCLK frequency */ + CGU_PERI = ((CGU_PERI & ~0x7F) | /* reset divider & clksel bits */ + (AS3525_PCLK_DIV0 << 2) | + (AS3525_PCLK_DIV1 << 6) | + AS3525_PCLK_SEL); + +#ifdef HAVE_MULTIDRIVE + /* Set uSD frequency */ + sd_set_unboosted_divider(); +#endif asm volatile( "mrc p15, 0, r0, c1, c0 \n" "bic r0, r0, #3<<30 \n" /* fastbus clocking */ @@ -387,7 +425,7 @@ /* FCLK is unused so put it to the lowest freq we can */ CGU_PROC = ((0xf << 4) | (0x3 << 2) | AS3525_CLK_MAIN); -#ifdef HAVE_ADJUSTABLE_CPU_VOLTAGE +#if defined(HAVE_ADJUSTABLE_CPU_VOLTAGE) && (CPUFREQ_MAX > 200000000) /* Decreasing frequency so reduce voltage after change */ ascodec_write(AS3514_CVDD_DCDC3, (AS314_CP_DCDC3_SETTING | CVDD_1_10)); #endif /* HAVE_ADJUSTABLE_CPU_VOLTAGE */ Index: debug-as3525.c =================================================================== --- debug-as3525.c (revision 28932) +++ debug-as3525.c (working copy) @@ -182,7 +182,12 @@ return 0; } case CLK_I2C: - return calc_freq(CLK_PCLK)/AS3525_I2C_PRESCALER; +#if CONFIG_CPU == AS3525 + if (cpu_frequency == CPUFREQ_MAX) + return calc_freq(CLK_PCLK)/AS3525_I2C_PRESCALER_BOOSTED; + else +#endif + return calc_freq(CLK_PCLK)/AS3525_I2C_PRESCALER; case CLK_I2SI: switch((CGU_AUDIO>>12) & 3) { case 0: @@ -218,7 +223,7 @@ case CLK_SD_MCLK_MSD: if(!(MCI_SD & (1<<8))) return 0; - else if(MCI_SD & (1<<10)) + else if(MCI_SD & (1<<10)) /* bypass */ return calc_freq(CLK_PCLK); else return calc_freq(CLK_PCLK)/(((MCI_SD & 0xff)+1)*2); @@ -289,21 +294,21 @@ lcd_puts(0, line++, "[Clock Frequencies:]"); lcd_puts(0, line++, " SET ACTUAL"); #if CONFIG_CPU == AS3525 - lcd_putsf(0, line++, "922T:%s %3dMHz", + lcd_putsf(0, line++, "922T:%s %6dKHz", (!(read_cp15()>>30)) ? "FAST " : (read_cp15()>>31) ? "ASYNC" : "SYNC ", #else - lcd_putsf(0, line++, "926ejs: %3dMHz", + lcd_putsf(0, line++, "926ejs: %6dKHz", #endif - calc_freq(CLK_PROC)/1000000); - lcd_putsf(0, line++, "PLLA:%3dMHz %3dMHz", AS3525_PLLA_FREQ/1000000, - calc_freq(CLK_PLLA)/1000000); - lcd_putsf(0, line++, "PLLB: %3dMHz", calc_freq(CLK_PLLB)/1000000); - lcd_putsf(0, line++, "FCLK: %3dMHz", calc_freq(CLK_FCLK)/1000000); - lcd_putsf(0, line++, "DRAM:%3dMHz %3dMHz", AS3525_PCLK_FREQ/1000000, - calc_freq(CLK_EXTMEM)/1000000); - lcd_putsf(0, line++, "PCLK:%3dMHz %3dMHz", AS3525_PCLK_FREQ/1000000, - calc_freq(CLK_PCLK)/1000000); + calc_freq(CLK_PROC)/1000); + lcd_putsf(0, line++, "PLLA:%6dKHz %6dKHz", AS3525_PLLA_FREQ/1000, + calc_freq(CLK_PLLA)/1000); + lcd_putsf(0, line++, "PLLB: %6dKHz", calc_freq(CLK_PLLB)/1000); + lcd_putsf(0, line++, "FCLK: %6dKHz", calc_freq(CLK_FCLK)/1000); + lcd_putsf(0, line++, "DRAM:%6dKHz %6dKHz", AS3525_PCLK_FREQ/1000, + calc_freq(CLK_EXTMEM)/1000); + lcd_putsf(0, line++, "PCLK:%6dKHz %6dKHz", AS3525_PCLK_FREQ/1000, + calc_freq(CLK_PCLK)/1000); #if LCD_HEIGHT < 176 /* clip */ lcd_update(); @@ -319,16 +324,16 @@ line = 0; #endif /* LCD_HEIGHT < 176 */ - lcd_putsf(0, line++, "IDE :%3dMHz %3dMHz", AS3525_IDE_FREQ/1000000, - calc_freq(CLK_IDE)/1000000); - lcd_putsf(0, line++, "DBOP:%3dMHz %3dMHz", AS3525_DBOP_FREQ/1000000, - calc_freq(CLK_DBOP)/1000000); - lcd_putsf(0, line++, "I2C :%3dkHz %3dkHz", AS3525_I2C_FREQ/1000, + lcd_putsf(0, line++, "IDE :%6dKHz %6dKHz", AS3525_IDE_FREQ/1000, + calc_freq(CLK_IDE)/1000); + lcd_putsf(0, line++, "DBOP:%6dKHz %6dKHz", AS3525_DBOP_FREQ/1000, + calc_freq(CLK_DBOP)/1000); + lcd_putsf(0, line++, "I2C :%6dkHz %6dkHz", AS3525_I2C_FREQ/1000, calc_freq(CLK_I2C)/1000); - lcd_putsf(0, line++, "I2SI: %s %3dMHz", (CGU_AUDIO & (1<<23)) ? - "on " : "off" , calc_freq(CLK_I2SI)/1000000); - lcd_putsf(0, line++, "I2SO: %s %3dMHz", (CGU_AUDIO & (1<<11)) ? - "on " : "off", calc_freq(CLK_I2SO)/1000000); + lcd_putsf(0, line++, "I2SI: %s %6dKHz", (CGU_AUDIO & (1<<23)) ? + "on " : "off" , calc_freq(CLK_I2SI)/1000); + lcd_putsf(0, line++, "I2SO: %s %6dKHz", (CGU_AUDIO & (1<<11)) ? + "on " : "off", calc_freq(CLK_I2SO)/1000); #if CONFIG_CPU == AS3525 /* If disabled, enable SD cards so we can read the registers */ if(sd_enabled == false) @@ -341,18 +346,18 @@ sd_enable(false); } - lcd_putsf(0, line++, "SD :%3dMHz %3dMHz", - ((AS3525_IDE_FREQ/ 1000000) / + lcd_putsf(0, line++, "SD :%6dKHz %6dKHz", + ((AS3525_IDE_FREQ/ 1000) / ((last_nand & MCI_CLOCK_BYPASS)? 1:(((last_nand & 0xff)+1) * 2))), - calc_freq(CLK_SD_MCLK_NAND)/1000000); + calc_freq(CLK_SD_MCLK_NAND)/1000); #ifdef HAVE_MULTIDRIVE - lcd_putsf(0, line++, "uSD :%3dMHz %3dMHz", - ((AS3525_PCLK_FREQ/ 1000000) / + lcd_putsf(0, line++, "uSD :%6dKHz %6dKHz", + ((calc_freq(CLK_PCLK)/ 1000) / ((last_sd & MCI_CLOCK_BYPASS) ? 1: (((last_sd & 0xff) + 1) * 2))), - calc_freq(CLK_SD_MCLK_MSD)/1000000); + calc_freq(CLK_SD_MCLK_MSD)/1000); #endif #endif /* CONFIG_CPU == AS3525 */ - lcd_putsf(0, line++, "USB : %3dMHz", calc_freq(CLK_USB)/1000000); + lcd_putsf(0, line++, "USB : %6dKHz", calc_freq(CLK_USB)/1000); #if LCD_HEIGHT < 176 /* clip */ lcd_update(); Index: clock-target.h =================================================================== --- clock-target.h (revision 28932) +++ clock-target.h (working copy) @@ -114,17 +114,19 @@ /* *5/8 = 240MHz 120, 80, 60, 48, 40 */ //#define AS3525_PLLA_SETTING 0x2630 -#define AS3525_FCLK_PREDIV 0 /* div = (8-n)/8 Enter manually & postdiv will be calculated*/ +#define AS3525_FCLK_PREDIV 2 /* div = (8-n)/8 Enter manually & postdiv will be calculated*/ /* 0 gives you the PLLA 1st line choices, 1 the 2nd line etc. */ -#define AS3525_FCLK_FREQ 248000000 /* Boosted FCLK frequency */ -#define AS3525_DRAM_FREQ 62000000 /* Initial DRAM frequency */ +#define AS3525_FCLK_FREQ 186000000 /* Boosted FCLK frequency - over 200MHz */ + /* requires CVDDp bumped to 1.2V */ +#define AS3525_DRAM_FREQ 24800000 /* Initial DRAM frequency */ +#define AS3525_DRAM_FREQ_BOOSTED 49600000 /* AS3525_PCLK_FREQ != AS3525_DRAM_FREQ/1 will boot to white lcd screen */ #endif /* CONFIG_CPU == AS3525v2 */ #define AS3525_PCLK_FREQ (AS3525_DRAM_FREQ/1) /* PCLK divided from DRAM freq */ - +#define AS3525_PCLK_FREQ_BOOSTED (AS3525_DRAM_FREQ_BOOSTED/1) #define AS3525_DBOP_FREQ (AS3525_PCLK_FREQ/1) /* DBOP divided from PCLK freq */ /** ****************************************************************************/ @@ -169,6 +171,9 @@ /*unable to use AS3525_PCLK_DIV1 != 0 successfuly so far*/ #define AS3525_PCLK_DIV1 (CLK_DIV(AS3525_DRAM_FREQ, AS3525_PCLK_FREQ) - 1)/* div = 1/(n+1)*/ #define AS3525_PCLK_DIV0 (CLK_DIV(AS3525_PLLA_FREQ, AS3525_DRAM_FREQ) - 1) /*div=1/(n+1)*/ +#define AS3525_PCLK_DIV1_BOOSTED (CLK_DIV(AS3525_DRAM_FREQ_BOOSTED, AS3525_PCLK_FREQ_BOOSTED) - 1) +#define AS3525_PCLK_DIV0_BOOSTED (CLK_DIV(AS3525_PLLA_FREQ, AS3525_PCLK_FREQ_BOOSTED) - 1) + #else #define AS3525_PCLK_SEL AS3525_CLK_FCLK @@ -179,8 +184,10 @@ /* PCLK as Source */ #define AS3525_DBOP_DIV (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1) /*div=1/(n+1)*/ #define AS3525_I2C_PRESCALER CLK_DIV(AS3525_PCLK_FREQ, AS3525_I2C_FREQ) + #define AS3525_I2C_PRESCALER_BOOSTED CLK_DIV(AS3525_PCLK_FREQ_BOOSTED, AS3525_I2C_FREQ) #define AS3525_I2C_FREQ 400000 #define AS3525_SD_IDENT_DIV ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SD_IDENT_FREQ) / 2) - 1) + #define AS3525_SD_IDENT_DIV_BOOSTED ((CLK_DIV(AS3525_PCLK_FREQ_BOOSTED, AS3525_SD_IDENT_FREQ) / 2) - 1) #define AS3525_SD_IDENT_FREQ 400000 /* must be between 100 & 400 kHz */ #define AS3525_SSP_PRESCALER ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SSP_FREQ) + 1) & ~1) /* must be an even number */ #define AS3525_SSP_FREQ 12000000 Index: sd-as3525.c =================================================================== --- sd-as3525.c (revision 28932) +++ sd-as3525.c (working copy) @@ -116,9 +116,8 @@ static tCardInfo card_info[NUM_DRIVES]; /* maximum timeouts recommanded in the SD Specification v2.00 */ -#define SD_MAX_READ_TIMEOUT ((AS3525_PCLK_FREQ) / 1000 * 100) /* 100 ms */ -#define SD_MAX_WRITE_TIMEOUT ((AS3525_PCLK_FREQ) / 1000 * 250) /* 250 ms */ - +#define SD_MAX_READ_TIMEOUT ((AS3525_PCLK_FREQ*(cpu_frequency==CPUFREQ_MAX?2:1)) / 1000 * 100) /* 100 ms */ +#define SD_MAX_WRITE_TIMEOUT ((AS3525_PCLK_FREQ*(cpu_frequency==CPUFREQ_MAX?2:1)) / 1000 * 250) /* 250 ms */ /* for compatibility */ static long last_disk_activity = -1; @@ -140,6 +139,8 @@ static volatile unsigned int transfer_error[NUM_VOLUMES]; #define PL180_MAX_TRANSFER_ERRORS 10 +extern long cpu_frequency; + #define UNALIGNED_NUM_SECTORS 10 static unsigned char aligned_buffer[UNALIGNED_NUM_SECTORS* SD_BLOCK_SIZE] __attribute__((aligned(32))); /* align on cache line size */ static unsigned char *uncached_buffer = AS3525_UNCACHED_ADDR(&aligned_buffer[0]); @@ -274,6 +275,7 @@ } else if(status & MCI_CMD_SENT) /* CMD sent, no response required */ return true; + udelay(1); } return false; @@ -283,7 +285,7 @@ #define MCI_HALFSPEED (MCI_CLOCK_ENABLE) /* MCLK/2 */ #define MCI_QUARTERSPEED (MCI_CLOCK_ENABLE | 1) /* MCLK/4 */ #define MCI_IDENTSPEED (MCI_CLOCK_ENABLE | AS3525_SD_IDENT_DIV) /* IDENT */ - +#define MCI_IDENTSPEED_BOOSTED (MCI_CLOCK_ENABLE | AS3525_SD_IDENT_DIV_BOOSTED) static int sd_init_card(const int drive) { unsigned long response; @@ -293,7 +295,10 @@ card_info[drive].rca = 0; /* MCLCK on and set to 400kHz ident frequency */ - MCI_CLOCK(drive) = MCI_IDENTSPEED; + if (cpu_frequency == CPUFREQ_MAX) + MCI_CLOCK(drive) = MCI_IDENTSPEED_BOOSTED; + else + MCI_CLOCK(drive) = MCI_IDENTSPEED; /* 100 - 400kHz clock required for Identification Mode */ /* Start of Card Identification Mode ************************************/ @@ -375,8 +380,12 @@ MCI_CLOCK(drive) = MCI_HALFSPEED; /* MCICLK = IDE_CLK/2 = 25 MHz */ #if defined(HAVE_MULTIDRIVE) else - /* MCICLK = PCLK/2 = 31MHz(HS) or PCLK/4 = 15.5 Mhz (STD)*/ - MCI_CLOCK(drive) = (hs_card ? MCI_HALFSPEED : MCI_QUARTERSPEED); + { /* PCLK = 23.25Mhz (46.5MHz boosted) MCI = 23.25Mhz(hs) or 11.625 */ + if (cpu_frequency == CPUFREQ_MAX ) + MCI_CLOCK(drive) = (hs_card ? MCI_FULLSPEED : MCI_HALFSPEED); + else + MCI_CLOCK(drive) = MCI_FULLSPEED; + } #endif /* CMD7 w/rca: Select card to put it in TRAN state */ @@ -523,6 +532,19 @@ } } +#ifdef HAVE_MULTIDRIVE +void sd_set_boosted_divider(void) +{ + MCI_CLOCK(SD_SLOT_AS3525) = (hs_card ? + MCI_FULLSPEED : MCI_HALFSPEED); +} + +void sd_set_unboosted_divider(void) +{ + MCI_CLOCK(SD_SLOT_AS3525) = MCI_FULLSPEED; +} +#endif + static void init_pl180_controller(const int drive) { MCI_COMMAND(drive) = MCI_DATA_CTRL(drive) = 0;