• Status Closed
  • Percent Complete
  • Task Type Patches
  • Category Configuration
  • Assigned To No-one
  • Operating System iPod Nano 2G
  • Severity Low
  • Priority Very Low
  • Reported Version Release 3.7.1
  • Due in Version Undecided
  • Due Date Undecided
  • Votes
  • Private
Attached to Project: Rockbox
Opened by Buschel - 2010-11-29
Last edited by Buschel - 2010-12-30

FS#11782 - iPod nano 2G: DRAM and clock settings

This patch does two things
a) Raising the boosted clock to the max allowed (CPU = 200.7 MHz, HCLK = CPU/2, PCLK = HCLK/4). The unboosted clock is using 200.7/4 for CPU/HLCK/PCLK.
b) Using mainly two different DRAM settings (MIUSDPARA) for boosted and unboosted clock. Those were derived from the data sheets of S5L8700 CPU and the K4M56163PG DRAM. To ensure proper startup crt0.s uses the Apple FWs DRAM configuration.

The raised CPU clock allows +4% of maximum CPU speed. Additionally the changed DRAM settings will speed up DRAM write by 10% (boosted) or 40% (nboosted). The DRAM settings do not have any (or very minor) impact to the speed of DRAM read and IRAM access.

Closed by  Buschel
2010-12-30 20:26
Reason for closing:  Accepted
Additional comments about closing:   Warning: Undefined array key "typography" in /home/rockbox/flyspray/plugins/dokuwiki/inc/parserutils.php on line 371 Warning: Undefined array key "camelcase" in /home/rockbox/flyspray/plugins/dokuwiki/inc/parserutils.php on line 407

Submitted with r28935.

battery bench for the above patch. I do not have a bench based on current svn, but using a bench based on a svn build before “lcd sleep” to extrapolate the overall runtime (runtime before 99% and beyond 4%) the runtime might be reduced by ~1h against current svn. If this is due to the DRAM settings or the higher clock cannot be derived from this bench.

Measurements based on averaged pmu_read_battery_current(), whereas DRAM old = svn, DRAM new = patched timings from above:

MHz | DRAM new | DRAM old
48 –.- 19.5 mA (idle)
48* 19.9 20.0 mA (* mpc decoding)
50 19.7 19.9 mA (idle)
50* 20.2 –.- mA (* mpc decoding)

MHz | DRAM new | DRAM old
192 –.- 24.0 mA
192* 24.5 24.4 mA
201 24.6 24.6 mA
201* 24.9 –.- mA

The DRAM timing themselves do not raise the current consumption. There is small increase of ~0.4-0.6 mA due to the higher clock.

Updated against r28793.

Updated against r28914.

The timings for the DRAM K4M56163PG are as follows:
CAS latency: 3
Row active to row active time: 18 ns
RAS-to-CAS read latency: 27 ns
RAS-to-CAS write latency: 27 ns
Row precharge time: 27 ns
Row active time: 50 ns
Row cycle time: 80 ns

From S5L8700 data sheet MIUSDPARA bits are:
[24..22] = CAS latency [cycles]
[20..19] = row active to row active - 1 [cycles]
[18..16] = RAS-to-CAS read latency - 1 [cycles]
[15..13] = RAS-to-CAS write latency - 1 [cycles]
[12..10] = row precharge time - 1 [cycles]
[9..6] = row active time - 1 [cycles]
[5..2] = row cycle time - 1 [cycles]
[1..0] = mode register set time - 1 [cycles] (default 0×01)

For 100 (96) MHz this results in 0x006A491D, for 50 (48) MHz in 0x0061248D.

This patch uses the OF’s default for MIUSDPARA in boosted state. The DRAM setting for unboosted is derived from this. All three targets (2 Meizus, 1 nano2G) are supported.


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